公开(公告)号：US12025917B2

公开(公告)日：2024-07-02

申请号：US16716792

申请日：2019-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Zhan Zhou ,  Heng-Jen Lee ,  Hsu-Yuan Liu ,  Yu-Chen Huang ,  Cheng-Han Wu ,  Shih-Che Wang ,  Ho-Yung David Hwang

IPC: G03F7/16 ,  B67D7/02 ,  B67D7/36 ,  B67D7/78 ,  H01L21/027

CPC classification number: G03F7/16 ,  B67D7/0294 ,  B67D7/36 ,  B67D7/78 ,  H01L21/0274 ,  Y10T137/0318 ,  Y10T137/86187

Abstract: A method of supplying a chemical solution to a photolithography system. The chemical solution is pumped from a variable-volume buffer tank. The pumped chemical solution is dispensed in a spin-coater. The variable-volume buffer tank is refilled by emptying a storage container filled with the chemical solution into the variable-volume buffer tank.

公开(公告)号：US11769678B2

公开(公告)日：2023-09-26

申请号：US17100218

申请日：2020-11-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tzu-Yang Lin ,  Cheng-Han Wu ,  Chen-Yu Liu ,  Kuo-Shu Tseng ,  Shang-Sheng Li ,  Chen Yi Hsu ,  Yu-Cheng Chang

IPC: H01L21/67

CPC classification number: H01L21/67242 ,  H01L21/67023

Abstract: A lithography includes a storage tank that stores process chemical fluid, an anti-collision frame, and an integrated sensor assembly. The storage tank includes a dispensing port positioned at a lowest part of the storage tank in a gravity direction. The anti-collision frame is coupled to the storage tank. An integrated sensor assembly is disposed on at least one of the anti-collision frame and the storage tank to measure a variation in fluid quality in response to fluid quality measurement of fluid.

公开(公告)号：US20230251571A1

公开(公告)日：2023-08-10

申请号：US18302608

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Keng-Chu Lin ,  Joung-Wei Liou ,  Cheng-Han Wu ,  Ya Hui Chang

IPC: G03F7/038 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3213 ,  G03F7/039 ,  G03F7/11 ,  G03F7/16 ,  G03F7/20 ,  G03F7/32

CPC classification number: G03F7/0388 ,  G03F7/038 ,  H01L21/0271 ,  H01L21/31144 ,  H01L21/32139 ,  G03F7/0382 ,  G03F7/0397 ,  G03F7/11 ,  G03F7/167 ,  G03F7/2041 ,  G03F7/322 ,  G03F7/325

Abstract: A system and method for depositing a photoresist and utilizing the photoresist are provided. In an embodiment a deposition chamber is utilized along with a first precursor material comprising carbon-carbon double bonds and a second precursor material comprising repeating units to deposit the photoresist onto a substrate. The first precursor material is turned into a plasma in a remote plasma chamber prior to being introduced into the deposition chamber. The resulting photoresist comprises a carbon backbone with carbon-carbon double bonds.

公开(公告)号：US10517179B2

公开(公告)日：2019-12-24

申请号：US15621646

申请日：2017-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Siao-Shan Wang ,  Cheng-Han Wu ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: H01L21/027 ,  H05K3/06 ,  G03F7/09 ,  G03F7/00 ,  G03F7/20 ,  G03F7/40

Abstract: Provided is a material composition and method that includes forming a patterned resist layer on a substrate. The patterned resist layer has a first pattern width, and the patterned resist layer has a first pattern profile having a first proportion of active sites. In some examples, the patterned resist layer is coated with a treatment material. In some embodiments, the treatment material bonds to surfaces of the patterned resist layer to provide a treated patterned resist layer having a second pattern profile with a second proportion of active sites greater than the first proportion of active sites. By way of example, and as part of the coating the patterned resist layer with the treatment material, a first pattern shrinkage process may be performed, where the treated patterned resist layer has a second pattern width less than a first pattern width.

公开(公告)号：US10157800B2

公开(公告)日：2018-12-18

申请号：US15635308

申请日：2017-06-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuei-Ming Chang ,  Rei-Jay Hsieh ,  Cheng-Han Wu ,  Chie-Iuan Lin

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a substrate, a first source/drain feature, a second source/drain feature and a dielectric plug. The substrate has a semiconductor fin. The first source/drain feature is embedded in the semiconductor fin. The second source/drain feature is embedded in the semiconductor fin. The dielectric plug extends from above the semiconductor fin into the semiconductor fin. The dielectric plug is in between the first source/drain feature and the second source/drain feature. The dielectric plug is separated from the first source/drain feature and the second source/drain feature.

公开(公告)号：US12222654B2

公开(公告)日：2025-02-11

申请号：US17378507

申请日：2021-07-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Hui Weng ,  Chen-Yu Liu ,  Cheng-Han Wu ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/32 ,  G03F1/82 ,  G03F7/00 ,  G03F7/30 ,  G03F7/40

Abstract: A method includes illuminating radiation to a resist layer over a substrate to pattern the resist layer. The patterned resist layer is developed by using a positive tone developer. The patterned resist layer is rinsed using a basic aqueous rinse solution. A pH value of the basic aqueous rinse solution is lower than a pH value of the developer, and a rinse temperature of rinsing the patterned resist layer is in a range of about 20° C. to about 40° C.

公开(公告)号：US11581227B2

公开(公告)日：2023-02-14

申请号：US17384888

申请日：2021-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuei-Ming Chang ,  Rei-Jay Hsieh ,  Cheng-Han Wu ,  Chie-Iuan Lin

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: An IC structure includes a semiconductor fin, first and second gate structures, and an isolation structure. The semiconductor fin extends from a substrate. The first gate structure extends above a top surface of the semiconductor fin by a first gate height. The second gate structure is over the semiconductor fin. The isolation structure is between the first and second gate structures, and has a lower dielectric portion embedded in the semiconductor fin and an upper dielectric portion extending above the top surface of the semiconductor fin by a height that is the same as the first gate height. When viewed in a cross section taken along a longitudinal direction of the semiconductor fin, the upper dielectric portion of the isolation structure has a rectangular profile with a width greater than a bottom width of the lower dielectric portion of the isolation structure.

公开(公告)号：US11075125B2

公开(公告)日：2021-07-27

申请号：US16933088

申请日：2020-07-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuei-Ming Chang ,  Rei-Jay Hsieh ,  Cheng-Han Wu ,  Chie-Iuan Lin

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: A device includes a semiconductor fin, a first transistor, a second transistor and a dielectric structure. The first semiconductor fin extends from a substrate. The first transistor is formed on a first region of the semiconductor fin. The second transistor is formed on a second region of the semiconductor fin laterally spaced apart from the first region of the semiconductor fin. The dielectric structure has a lower portion extending in the semiconductor fin and between the first transistor and the second transistor. The lower portion of the dielectric structure has a width increasing from a bottommost position of the dielectric structure to a first position higher than the bottommost position of the dielectric structure and decreasing from the first position to a second position higher than the first position.

公开(公告)号：US11037820B2

公开(公告)日：2021-06-15

申请号：US16719596

申请日：2019-12-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tzu-Yang Lin ,  Cheng-Han Wu ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/033 ,  H01L21/027

Abstract: A method for forming openings in an underlayer includes: forming a photoresist layer on an underlayer formed on a substrate; exposing the photoresist layer; forming photoresist patterns by developing the exposed photoresist layer, the photoresist patterns covering regions of the underlayer in which the openings are to be formed; forming a liquid layer over the photoresist patterns; after forming the liquid layer, performing a baking process so as to convert the liquid layer to an organic layer in a solid form; performing an etching back process to remove a portion of the organic layer on a level above the photoresist patterns; removing the photoresist patterns, so as to expose portions of the underlayer by the remaining portion of the organic layer; forming the openings in the underlayer by using the remaining portion of the organic layer as an etching mask; and removing the remaining portion of the organic layer.

公开(公告)号：US10863630B2

公开(公告)日：2020-12-08

申请号：US16723818

申请日：2019-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Siao-Shan Wang ,  Cheng-Han Wu ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: H05K3/06 ,  G03F7/09 ,  H01L21/027 ,  G03F7/00 ,  G03F7/20 ,  G03F7/40

Abstract: Provided is a material composition and method that includes forming a patterned resist layer on a substrate. The patterned resist layer has a first pattern width, and the patterned resist layer has a first pattern profile having a first proportion of active sites. In some examples, the patterned resist layer is coated with a treatment material. In some embodiments, the treatment material bonds to surfaces of the patterned resist layer to provide a treated patterned resist layer having a second pattern profile with a second proportion of active sites greater than the first proportion of active sites. By way of example, and as part of the coating the patterned resist layer with the treatment material, a first pattern shrinkage process may be performed, where the treated patterned resist layer has a second pattern width less than a first pattern width.