公开(公告)号：US20220013422A1

公开(公告)日：2022-01-13

申请号：US16924208

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mao-Yen Chang ,  Chih-Wei Lin ,  Hao-Yi Tsai ,  Kuo-Lung Pan ,  Chun-Cheng Lin ,  Tin-Hao Kuo ,  Yu-Chia Lai ,  Chih-Hsuan Tai

IPC: H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/40 ,  H01L23/538 ,  H01L23/498 ,  H01L25/00

Abstract: Provided is a package structure including a composite wafer, a plurality of dies, an underfill, and a plurality of dam structures. The composite wafer has a first surface and a second surface opposite to each other. The composite wafer includes a plurality of seal rings dividing the composite wafer into a plurality of packages; and a plurality of through holes respectively disposed between the seal rings and penetrating through the first and second surfaces. The dies are respectively bonded onto the packages at the first surface by a plurality of connectors. The underfill laterally encapsulates the connectors. The dam structures are disposed on the first surface of the composite wafer to separate the underfill from the through holes.

公开(公告)号：US09978716B2

公开(公告)日：2018-05-22

申请号：US15237428

申请日：2016-08-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Chiang Tsao ,  Hsiu-Jen Lin ,  Chun-Cheng Lin ,  Chih-Wei Lin ,  Ming-Da Cheng ,  Ching-Hua Hsieh ,  Chung-Shi Liu

IPC: H01L23/48 ,  H01L25/065 ,  H01L21/48 ,  H01L21/50 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L25/00 ,  H01L21/60

CPC classification number: H01L25/0652 ,  H01L21/486 ,  H01L21/50 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/5387 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2021/6003 ,  H01L2021/60052 ,  H01L2021/6009 ,  H01L2021/60247 ,  H01L2021/60255 ,  H01L2221/68331 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2221/68372 ,  H01L2224/02331 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/83

Abstract: A package structure includes a molding material, at least one through-via, at least one conductor, at least one dummy structure and an underfill. The through-via extends through the molding material. The conductor is present on the through-via. The dummy structure is present on the molding material and includes a dielectric material. The underfill is at least partially present between the conductor and the dummy structure.

公开(公告)号：US09287233B2

公开(公告)日：2016-03-15

申请号：US14093856

申请日：2013-12-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Liang Chen ,  Wei-Ting Lin ,  Kuan-Lin Ho ,  Yu-Chih Liu ,  Chun-Cheng Lin ,  Shih-Yen Lin

IPC: H01L23/12 ,  H01L23/34 ,  H01L23/10 ,  H01L23/00 ,  H01L23/42 ,  H01L23/367

CPC classification number: H01L24/81 ,  H01L23/10 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81 ,  H01L2224/83455 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2224/92225 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16251 ,  H01L2924/164 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L21/563

Abstract: The present disclosure relates to an integrated chip package having a plurality of different adhesive layers that provide for a low lid induced stress good warpage control of a substrate and/or IC die, and an associated method of formation. The integrated chip package has an integrated chip (IC) die coupled to an underlying substrate by an electrically conductive interconnect structure. A first adhesive layer, having a first Young's modulus, is disposed onto the substrate at a first plurality of positions surrounding the IC die. A second adhesive layer, having a second Young's modulus different than the first Young's modulus, is disposed onto the substrate at a second plurality of positions surrounding the IC die. A lid is affixed to the substrate by the first and second adhesive layers and extends to a position overlying the IC die.

Abstract translation: 本公开涉及具有多个不同粘合剂层的集成芯片封装，其提供用于衬底和/或IC芯片的低盖诱导应力良好翘曲控制以及相关联的形成方法。 集成芯片封装具有通过导电互连结构耦合到下面的衬底的集成芯片（IC）裸芯片。 具有第一杨氏模量的第一粘合剂层在围绕IC管芯的第一多个位置处设置在基板上。 具有不同于第一杨氏模量的第二杨氏模量的第二粘合层在围绕IC管芯的第二多个位置处设置在基板上。 盖通过第一和第二粘合剂层固定到基底上，并延伸到覆盖IC芯片的位置。

公开(公告)号：US20150155221A1

公开(公告)日：2015-06-04

申请号：US14093856

申请日：2013-12-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Liang Chen ,  Wei-Ting Lin ,  Kuan-Lin Ho ,  Yu-Chih Liu ,  Chun-Cheng Lin ,  Shih-Yen Lin

IPC: H01L23/433 ,  H01L23/00 ,  H01L23/16 ,  H01L23/02 ,  H01L21/52 ,  H01L21/56

CPC classification number: H01L24/81 ,  H01L23/10 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81 ,  H01L2224/83455 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2224/92225 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16251 ,  H01L2924/164 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L21/563

Abstract: The present disclosure relates to an integrated chip package having a plurality of different adhesive layers that provide for a low lid induced stress good warpage control of a substrate and/or IC die, and an associated method of formation. The integrated chip package has an integrated chip (IC) die coupled to an underlying substrate by an electrically conductive interconnect structure. A first adhesive layer, having a first Young's modulus, is disposed onto the substrate at a first plurality of positions surrounding the IC die. A second adhesive layer, having a second Young's modulus different than the first Young's modulus, is disposed onto the substrate at a second plurality of positions surrounding the IC die. A lid is affixed to the substrate by the first and second adhesive layers and extends to a position overlying the IC die.

Abstract translation: 本公开涉及具有多个不同粘合剂层的集成芯片封装，其提供用于衬底和/或IC芯片的低盖诱导应力良好翘曲控制以及相关联的形成方法。 集成芯片封装具有通过导电互连结构耦合到下面的衬底的集成芯片（IC）裸芯片。 具有第一杨氏模量的第一粘合剂层在围绕IC管芯的第一多个位置处设置在基板上。 具有不同于第一杨氏模量的第二杨氏模量的第二粘合层在围绕IC管芯的第二多个位置处设置在基板上。 盖通过第一和第二粘合剂层固定到基底上，并延伸到覆盖IC芯片的位置。

公开(公告)号：US11456226B2

公开(公告)日：2022-09-27

申请号：US16858737

申请日：2020-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Cheng Lin ,  Ching-Hua Hsieh ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Chih-Wei Lin

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/367 ,  H01L23/29 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  B29C45/14 ,  B29K63/00 ,  B29L31/34

Abstract: A semiconductor package including a circuit substrate, an interposer structure, a plurality of dies, and an insulating encapsulant is provided. The interposer structure is disposed on the circuit substrate. The plurality of dies is disposed on the interposer structure, wherein the plurality of dies is electrically connected to the circuit substrate through the interposer structure. The insulating encapsulant is disposed on the circuit substrate, wherein the insulating encapsulant surrounds the plurality of dies and the interposer structure and encapsulates at least the interposer structure, the insulating encapsulant has a groove that surrounds the interposer structure and the plurality of dies, and the interposer structure and the plurality of dies are confined to be located within the groove.

公开(公告)号：US20190139845A1

公开(公告)日：2019-05-09

申请号：US15874890

申请日：2018-01-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Cheng Lin ,  Ching-Hua Hsieh ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Chih-Wei Lin

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/367 ,  H01L23/29 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package including a circuit substrate, an interposer structure, a plurality of dies, and an insulating encapsulant is provided. The interposer structure is disposed on the circuit substrate. The plurality of dies is disposed on the interposer structure, wherein the plurality of dies is electrically connected to the circuit substrate through the interposer structure. The insulating encapsulant is disposed on the circuit substrate, wherein the insulating encapsulant surrounds the plurality of dies and the interposer structure and encapsulates at least the interposer structure, the insulating encapsulant has a groove that surrounds the interposer structure and the plurality of dies, and the interposer structure and the plurality of dies are confined to be located within the groove.

公开(公告)号：US11322421B2

公开(公告)日：2022-05-03

申请号：US16924208

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mao-Yen Chang ,  Chih-Wei Lin ,  Hao-Yi Tsai ,  Kuo-Lung Pan ,  Chun-Cheng Lin ,  Tin-Hao Kuo ,  Yu-Chia Lai ,  Chih-Hsuan Tai

IPC: H01L23/40 ,  H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00

Abstract: Provided is a package structure including a composite wafer, a plurality of dies, an underfill, and a plurality of dam structures. The composite wafer has a first surface and a second surface opposite to each other. The composite wafer includes a plurality of seal rings dividing the composite wafer into a plurality of packages; and a plurality of through holes respectively disposed between the seal rings and penetrating through the first and second surfaces. The dies are respectively bonded onto the packages at the first surface by a plurality of connectors. The underfill laterally encapsulates the connectors. The dam structures are disposed on the first surface of the composite wafer to separate the underfill from the through holes.

公开(公告)号：US20210020581A1

公开(公告)日：2021-01-21

申请号：US16514987

申请日：2019-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsaing-Pin Kuan ,  Ching-Hua Hsieh ,  Chih-Wei Lin ,  Chun-Cheng Lin ,  Yu-Wei Lin ,  Chun-Yen Lan

IPC: H01L23/552 ,  H01L23/28 ,  H01L23/538 ,  H01L21/56 ,  H01L21/768

Abstract: A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes a first semiconductor die, an insulating encapsulation laterally encapsulating the first semiconductor die, an electromagnetic shielding structure enclosing the first semiconductor die and a first portion of the insulating encapsulation, and a redistribution structure. The electromagnetic shielding structure includes a first conductive layer and a dielectric frame laterally covering the first conductive layer. The first conductive layer surrounds the first portion of the insulating encapsulation and extends to cover a first side of the first semiconductor die. The dielectric frame includes a first surface substantially leveled with the first conductive layer. The redistribution structure is disposed on a second side of the first semiconductor die opposing to the first side, and the redistribution structure is electrically coupled to the first semiconductor die and the first conductive layer of the electromagnetic shielding structure.

公开(公告)号：US20200258801A1

公开(公告)日：2020-08-13

申请号：US16858737

申请日：2020-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Cheng Lin ,  Ching-Hua Hsieh ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Chih-Wei Lin

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/367 ,  H01L23/29 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package including a circuit substrate, an interposer structure, a plurality of dies, and an insulating encapsulant is provided. The interposer structure is disposed on the circuit substrate. The plurality of dies is disposed on the interposer structure, wherein the plurality of dies is electrically connected to the circuit substrate through the interposer structure. The insulating encapsulant is disposed on the circuit substrate, wherein the insulating encapsulant surrounds the plurality of dies and the interposer structure and encapsulates at least the interposer structure, the insulating encapsulant has a groove that surrounds the interposer structure and the plurality of dies, and the interposer structure and the plurality of dies are confined to be located within the groove.