Integrated circuit imaging, rendering and layout editing system and method

    公开(公告)号:US11593545B2

    公开(公告)日:2023-02-28

    申请号:US17443397

    申请日:2021-07-26

    Inventor: Dale Carlson

    Abstract: Described are various embodiments of a system and method for verifying extracted integrated circuit (IC) features representative of a source IC and stored in a feature dataset structure. Generally, a set of extracted IC features imaged within a designated IC area is converted into a static tile image. The static tile image is then rendered for visualization as an interactive mapping of the feature dataset structure within the area. Corrections for one or more of the set of extracted IC features are received based on the static tile image and input corrections are executed on the feature dataset structure to produce an updated feature dataset structure.

    Integrated circuit imaging, rendering and layout editing system and method

    公开(公告)号:US11074389B2

    公开(公告)日:2021-07-27

    申请号:US16692900

    申请日:2019-11-22

    Inventor: Dale Carlson

    Abstract: Described are various embodiments of a system and method for verifying extracted integrated circuit (IC) features representative of a source IC and stored in a feature dataset structure. Generally, a set of extracted IC features imaged within a designated IC area is converted into a static tile image. The static tile image is then rendered for visualization as an interactive mapping of the feature dataset structure within the area. Corrections for one or more of the set of extracted IC features are received based on the static tile image and input corrections are executed on the feature dataset structure to produce an updated feature dataset structure.

    INTEGRATED CIRCUIT IMAGING, RENDERING AND LAYOUT EDITING SYSTEM AND METHOD

    公开(公告)号:US20200167517A1

    公开(公告)日:2020-05-28

    申请号:US16692900

    申请日:2019-11-22

    Inventor: Dale Carlson

    Abstract: Described are various embodiments of a system and method for verifying extracted integrated circuit (IC) features representative of a source IC and stored in a feature dataset structure. Generally, a set of extracted IC features imaged within a designated IC area is converted into a static tile image. The static tile image is then rendered for visualization as an interactive mapping of the feature dataset structure within the area. Corrections for one or more of the set of extracted IC features are received based on the static tile image and input corrections are executed on the feature dataset structure to produce an updated feature dataset structure.

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