公开(公告)号：US10320406B2

公开(公告)日：2019-06-11

申请号：US15774455

申请日：2016-11-04

Applicant: Teledyne e2v Semiconductors SAS

Inventor： Etienne Bouin ,  Rémi Laube ,  Jérôme Ligozat ,  Marc Stackler

IPC: H03K5/00 ,  H03M1/06 ,  H03M1/12 ,  H04L7/00 ,  H03K5/1534

Abstract: In an architecture for processing data comprising a control unit and converters CNj to be synchronized to an active front of a common reference clock CLK, the synchronizing method makes provision for the converters to be arranged in at least one series chain, and for a procedure for synchronizing the converters by propagating a synchronizing signal SYNC-m emitted by the control unit, said signal being retransmitted as output OUT by each converter, after resynchronization to a clock active front, to a synchronization input IN of a following converter in the chain. Each converter comprises a synchronization configuration register REG containing at least one polarity parameter Sel-edgej that sets the polarity of the reference-clock front for reliable detection of a synchronizing signal received via the input of the converter. A phase parameter Sel-shiftj furthermore allows the phase of the sampling clocks of n converting cores of the converters, working at a sampling frequency obtained by dividing by n the CLK reference-clock frequency, to be synchronized.

公开(公告)号：US12009833B2

公开(公告)日：2024-06-11

申请号：US17636820

申请日：2020-08-19

Applicant: Teledyne e2v Semiconductors SAS

Inventor： Quentin Béraud-Sudreau ,  Jérôme Ligozat ,  Rémi Laube ,  Marc Stackler

IPC: H03M7/00 ,  G11C7/10 ,  H03K19/17736 ,  H03M1/12

CPC classification number: H03M1/1255 ,  G11C7/1036 ,  H03K19/1774 ,  H03M1/1215

Abstract: A method for synchronizing analog data (Data_ana1, Data_ana2) at the output of a plurality of digital/analog converters (DAC), comprising at least one conversion core (C1, C2), on an active edge of a common reference clock (Clk), the method comprising the following steps: a) supplying an external synchronization signal (SYNC_ext), to at least one converter, and supplying a signal of the common reference clock to the plurality of converters; b) generating, within each converter, an internal synchronization signal (SYNC_int), such that all the internal synchronization signals are aligned on an active edge of the common reference clock; c) for each of the converters, generating a start signal (START1, START2) which represents the start of the sending of digital data and counting a number of clock strokes until the internal synchronization signal is generated, and; d) applying a delay Ri (R1, R2) to each converter core, the delay being equal to the difference between the highest number counted in step c) and the number counted for the core. Device for implementing such a method.

公开(公告)号：US12040812B2

公开(公告)日：2024-07-16

申请号：US17636820

申请日：2020-08-19

Applicant: Teledyne e2v Semiconductors SAS

Inventor： Quentin Béraud-Sudreau ,  Jérôme Ligozat ,  Rémi Laube ,  Marc Stackler

IPC: H03M7/00 ,  G11C7/10 ,  H03K19/17736 ,  H03M1/12

CPC classification number: H03M1/1255 ,  G11C7/1036 ,  H03K19/1774 ,  H03M1/1215

Abstract: A method for synchronizing analog data (Data_ana1, Data_ana2) at the output of a plurality of digital/analog converters (DAC), comprising at least one conversion core (C1, C2), on an active edge of a common reference clock (Clk), the method comprising the following steps: a) supplying an external synchronization signal (SYNC_ext), to at least one converter, and supplying a signal of the common reference clock to the plurality of converters; b) generating, within each converter, an internal synchronization signal (SYNC_int), such that all the internal synchronization signals are aligned on an active edge of the common reference clock; c) for each of the converters, generating a start signal (START1, START2) which represents the start of the sending of digital data and counting a number of clock strokes until the internal synchronization signal is generated, and; d) applying a delay Ri (R1, R2) to each converter core, the delay being equal to the difference between the highest number counted in step c) and the number counted for the core. Device for implementing such a method.

公开(公告)号：US20220302922A1

公开(公告)日：2022-09-22

申请号：US17636820

申请日：2020-08-19

Applicant: Teledyne e2v Semiconductors SAS

Inventor： Quentin Béraud-Sudreau ,  Jérôme Ligozat ,  Rémi Laube ,  Marc Stackler

IPC: H03M1/12 ,  G11C7/10 ,  H03K19/17736

Abstract: A method for synchronizing analog data (Data_ana1, Data_ana2) at the output of a plurality of digital/analog converters (DAC), comprising at least one conversion core (C1, C2), on an active edge of a common reference clock (Clk), the method comprising the following steps: a) supplying an external synchronization signal (SYNC_ext), to at least one converter, and supplying a signal of the common reference clock to the plurality of converters; b) generating, within each converter, an internal synchronization signal (SYNC_int), such that all the internal synchronization signals are aligned on an active edge of the common reference clock; c) for each of the converters, generating a start signal (START1, START2) which represents the start of the sending of digital data and counting a number of clock strokes until the internal synchronization signal is generated, and; d) applying a delay Ri (R1, R2) to each converter core, the delay being equal to the difference between the highest number counted in step c) and the number counted for the core. Device for implementing such a method.