-
公开(公告)号：US11588667B2
公开(公告)日：2023-02-21
申请号：US17461575
申请日：2021-08-30
Applicant: Texas Instruments Incorporated
Inventor： Raghu Ganesan , Saravanakkumar Radhakrishnan , Gaurav Aggarwal
Abstract: An example apparatus includes: a feed forward equalizer (FFE) with a FFE output, adder circuitry with a first adder input, a second adder input, and a first adder output, the first adder input coupled to the FFE output, a multiplexer (MUX) with a first MUX input, a second MUX input, and a MUX output, the first MUX input coupled to the first adder output, the second MUX input coupled to the FFE output, a decision feedback equalizer (DFE) with a DFE output coupled to the second adder input, and a timing error detector (TED) with a first TED input coupled to the MUX output.
-
2.发明公开公开(公告)号：US20240106688A1
公开(公告)日：2024-03-28
申请号：US17954463
申请日：2022-09-28
Applicant: Texas Instruments Incorporated
Inventor： Saravanakkumar Radhakrishnan , Raghu Ganesan
CPC classification number: H04L25/03267 , H04L7/0062
Abstract: A network communications receiver and a method of operating the same in symbol timing recovery and equalization adaptation. A data converter samples a received analog signal at an initialization frequency higher than the symbol frequency of the received signal, and converts the samples to a digital sample stream. A decision feedback equalizer including a digital filter with one or more tap weights is adapted, and an error measurement obtained from the output of the decision feedback equalizer. In response to the error measurement crossing an error threshold value, a timing loop including timing error detection is initiated to adjust the phase of the sampling clock applied to the data converter.
-
公开(公告)号：US11595064B2
公开(公告)日：2023-02-28
申请号：US17401398
申请日：2021-08-13
Applicant: Texas Instruments Incorporated
Inventor： Raghu Ganesan , Saravanakkumar Radhakrishnan , Gaurav Aggarwal , Rallabandi V Lakshmi Annapurna
Abstract: A receiver circuit includes an analog-to-digital converter (ADC), a decision feedback equalizer (DFE), a slicer, and a timing error detector (TED). The DFE is coupled to the ADC, and includes a first tap and a second tap. The slicer is coupled to the DFE. The TED is coupled to the slicer. The TED is configured to initialize timing of a sampling clock provided to the ADC while initializing the second tap of the DFE and holding the first tap of the DFE at a constant value.
-
公开(公告)号：US12028192B2
公开(公告)日：2024-07-02
申请号：US18111862
申请日：2023-02-20
Applicant: Texas Instruments Incorporated
Inventor： Raghu Ganesan , Saravanakkumar Radhakrishnan , Gaurav Aggarwal
CPC classification number: H04L25/03057 , H04L7/0079 , H04L7/033
Abstract: An example apparatus includes: a feed forward equalizer (FFE) with a FFE output, adder circuitry with a first adder input, a second adder input, and a first adder output, the first adder input coupled to the FFE output, a multiplexer (MUX) with a first MUX input, a second MUX input, and a MUX output, the first MUX input coupled to the first adder output, the second MUX input coupled to the FFE output, a decision feedback equalizer (DFE) with a DFE output coupled to the second adder input, and a timing error detector (TED) with a first TED input coupled to the MUX output.
-
公开(公告)号：US20220070031A1
公开(公告)日：2022-03-03
申请号：US17461575
申请日：2021-08-30
Applicant: Texas Instruments Incorporated
Inventor： Raghu Ganesan , Saravanakkumar Radhakrishnan , Gaurav Aggarwal
Abstract: An example apparatus includes: a feed forward equalizer (FFE) with a FFE output, adder circuitry with a first adder input, a second adder input, and a first adder output, the first adder input coupled to the FFE output, a multiplexer (MUX) with a first MUX input, a second MUX input, and a MUX output, the first MUX input coupled to the first adder output, the second MUX input coupled to the FFE output, a decision feedback equalizer (DFE) with a DFE output coupled to the second adder input, and a timing error detector (TED) with a first TED input coupled to the MUX output.
-
Patent Agency Ranking
公开(公告)号：US12267182B2
公开(公告)日：2025-04-01
申请号：US18117511
申请日：2023-03-06
Applicant: Texas Instruments Incorporated
Inventor： Raghu Ganesan , Saravanakkumar Radhakrishnan , Gaurav Aggarwal
Abstract: A receiver circuit includes a feedback loop including a device. The receiver circuit also includes a register and a sequencer. The sequencer is configured to, responsive to an error signal being below a threshold value, cause the register to store a value indicative of the state of the feedback loop. The sequencer is also configured to cause the feedback loop to transition to a lower power state, and, responsive to a detected wake-up event, cause the previously stored value indicative of the state of the feedback loop to be loaded from the register into the device and enable the feedback loop.
-
公开(公告)号：US20230208685A1
公开(公告)日：2023-06-29
申请号：US18111862
申请日：2023-02-20
Applicant: Texas Instruments Incorporated
Inventor： Raghu Ganesan , Saravanakkumar Radhakrishnan , Gaurav Aggarwal
CPC classification number: H04L25/03057 , H04L7/0079 , H04L7/033
Abstract: An example apparatus includes: a feed forward equalizer (FFE) with a FFE output, adder circuitry with a first adder input, a second adder input, and a first adder output, the first adder input coupled to the FFE output, a multiplexer (MUX) with a first MUX input, a second MUX input, and a MUX output, the first MUX input coupled to the first adder output, the second MUX input coupled to the FFE output, a decision feedback equalizer (DFE) with a DFE output coupled to the second adder input, and a timing error detector (TED) with a first TED input coupled to the MUX output.
-
公开(公告)号：US11374601B2
公开(公告)日：2022-06-28
申请号：US17200426
申请日：2021-03-12
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Raghu Ganesan , Saravanakkumar Radhakrishnan , Kalpesh Laxmanbhai Rajai , Soumyajit Roul , Sumantra Seth
Abstract: A receiver circuit includes an interleaved ADC, a first delay circuit, a second delay circuit, a first processing channel, a second processing channel, and an interleaving ADC timing error detector circuit. The interleaved ADC includes a first ADC and a second ADC in parallel. The first delay circuit delays a first clock signal provided to the first ADC. The second delay circuit delays a second clock signal provided to the second ADC. The first processing channel processes data samples provided by the first ADC, and includes a first slicer. The second processing channel processes data samples provided by the second ADC, and includes a second slicer. The interleaving ADC timing error detector circuit controls delay of the first delay circuit and the second delay circuit based on an output signal of the first slicer, and an output signal or an input signal of the second slicer.
-
公开(公告)号：US11316707B2
公开(公告)日：2022-04-26
申请号：US17199142
申请日：2021-03-11
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Kalpesh Laxmanbhai Rajai , Saravanakkumar Radhakrishnan , Gaurav Aggarwal , Raghu Ganesan , Rallabandi V Lakshmi Annapurna
Abstract: A method includes receiving an input signal at a filter, where the filter includes a plurality of filter taps, and where each of a first filter tap and a second filter tap has a weighting coefficient. The method also includes shutting down the first filter tap based on the weighting coefficient of the first filter tap being below a threshold and the weighting coefficient of the second filter tap being below the threshold, where the second filter tap is next to the first filter tap.
-
公开(公告)号：US20230417529A1
公开(公告)日：2023-12-28
申请号：US18072458
申请日：2022-11-30
Applicant: Texas Instruments Incorporated
Inventor： Raghu Ganesan , Rallabandi Annapurna , Sucheth S. Kuncham , Saravanakkumar Radhakrishnan , Sumantra Seth , Geet Modi
IPC: G01B7/02
CPC classification number: G01B7/026
Abstract: An example first device includes: processor circuitry configured to establish a cable communication; analog to digital converter circuitry configured to sample cable voltages over time; echo estimator circuitry configured to determine a plurality of echo coefficients corresponding to the plurality of voltages; and physical length estimator circuitry configured to: identify a first echo coefficient in the echo coefficients that satisfies a static threshold, the first echo coefficient corresponding to a near end echo; identify a second echo coefficient in the echo coefficients that satisfies a dynamic threshold, the second echo coefficient corresponding to a far end echo; and estimate the length of a cable for the cable communication based on the first echo coefficient and the second echo coefficient.
-
-
-
-
-
-
-
-
-
Search Results
14
records
(took 0.02 seconds)
