公开(公告)号：US09436442B1

公开(公告)日：2016-09-06

申请号：US14097942

申请日：2013-12-05

Applicant: The MathWorks, Inc.

Inventor： Kiran Kintali ,  Anand Krishnamoorthi ,  Srinivas Muddana ,  Richard M. McKeever

IPC: G06F9/44 ,  H03M7/24

CPC classification number: G06F8/35 ,  G06F8/40 ,  H03M7/24 ,  H03M7/28

Abstract: A method and system for enabling a designer to more easily convert a model of a dynamic system instantiated using floating-point representation such as has been created in a high level design language to fixed-point code suitable for execution in a programmable processor or logic array.

Abstract translation: 一种用于使设计者能够更容易地将使用诸如已经以高级设计语言创建的浮点表示实例化的动态系统的模型转换成适于在可编程处理器或逻辑阵列中执行的定点代码的方法和系统 。

公开(公告)号：US08863069B1

公开(公告)日：2014-10-14

申请号：US13867768

申请日：2013-04-22

Applicant: The MathWorks, Inc.

Inventor： Girish Venkataramani ,  Kiran Kintali ,  Pieter J. Mosterman

IPC: G06F17/50

CPC classification number: G06F17/5045

Abstract: A system and method optimizes hardware description code generated from a graphical program or model automatically. The system may include a streaming optimizer, and a delay balancing engine. The streaming optimizer transforms one or more vector data paths in the source model to scalar data paths or to a smaller-sized vector data paths. The streaming optimizer may also configure portions of the modified model to execute at a faster rate. The delay balancing engine may examine the modified model to determine whether any delays or latencies have been introduced. If so, the delay balancing engine may insert one or more blocks into the modified model to correct for any data path misalignment caused by the introduction of the delays or latencies. A validation model, a report, or hardware description code that utilizes fewer hardware resources may be generated from the modified model.

公开(公告)号：US09298862B1

公开(公告)日：2016-03-29

申请号：US14245629

申请日：2014-04-04

Applicant: The MathWorks, Inc.

Inventor： Girish Venkataramani ,  Kiran Kintali

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F8/35 ,  G06F17/5045 ,  G06F17/5054

Abstract: A system and method optimizes hardware description generated from a graphical program or model automatically. The system may include a streaming optimizer, a resource sharing optimizer and a delay balancing engine. The streaming optimizer transforms one or more vector data paths in the source model to scalar data paths or to a smaller-sized vector data paths. The resource sharing optimizer may replace multiple blocks of the source model that are functionally equivalent with a single shared block. The streaming and resource sharing optimizers may also configure portions of the modified model to execute at a faster rate. The delay balancing engine may examine the modified model to determine whether any delays or latencies have been introduced. If so, the delay balancing engine may insert one or more blocks into the modified model to correct for any data path misalignment caused by the introduction of the delays or latencies. A validation model, a report, or hardware description code that utilizes fewer hardware resources may be generated from the modified model.

Abstract translation: 系统和方法自动优化从图形程序或模型生成的硬件描述。 系统可以包括流优化器，资源共享优化器和延迟平衡引擎。 流优化器将源模型中的一个或多个向量数据路径转换为标量数据路径或更小尺寸的向量数据路径。 资源共享优化器可以替换与单个共享块功能等同的源模型的多个块。 流和资源共享优化器还可以配置经修改的模型的部分以更快的速率执行。 延迟平衡引擎可以检查修改的模型以确定是否引入了任何延迟或延迟。 如果是这样，延迟平衡引擎可以将一个或多个块插入到经修改的模型中，以校正由引入延迟或延迟引起的任何数据路径未对准。 可以从修改的模型生成利用较少硬件资源的验证模型，报告或硬件描述代码。

公开(公告)号：US10248390B1

公开(公告)日：2019-04-02

申请号：US14993773

申请日：2016-01-12

Applicant: The MathWorks, Inc.

Inventor： Girish Venkataramani ,  Kiran Kintali

IPC: G06F17/50 ,  G06F8/35 ,  G06F8/34

Abstract: A system and method optimizes hardware description generated from a graphical program or model automatically. The system may include a streaming optimizer, a resource sharing optimizer and a delay balancing engine. The streaming optimizer transforms one or more vector data paths in the source model to scalar data paths or to a smaller-sized vector data paths. The resource sharing optimizer may replace multiple blocks of the source model that are functionally equivalent with a single shared block. The streaming and resource sharing optimizers may also configure portions of the modified model to execute at a faster rate. The delay balancing engine may examine the modified model to determine whether any delays or latencies have been introduced. If so, the delay balancing engine may insert one or more blocks into the modified model to correct for any data path misalignment caused by the introduction of the delays or latencies. A validation model, a report, or hardware description code that utilizes fewer hardware resources may be generated from the modified model.