公开(公告)号：US20200151088A1

公开(公告)日：2020-05-14

申请号：US16270082

申请日：2019-02-07

Applicant: The MathWorks, Inc.

Inventor： Yongfeng Gu ,  Girish Venkataramani ,  Wang Chen ,  Bharathi Yogaraj ,  Yuteng Zhou ,  Vibha Patil ,  Anusha Vasantala ,  Purshottam Vishwakarma

IPC: G06F11/36 ,  G06F8/41 ,  G06N3/063 ,  G06N7/00 ,  G06F15/78 ,  G06F5/06

Abstract: Systems and methods may configure a programmable logic device to efficiently run a deep learning (DL) network. Architecture code and algorithmic code may be generated. The architecture code may define convolutional and fully connected processor cores structured to run the layers of a Deep Neural Network (DNN). The processor cores may be interconnected by a First In First Out (FIFO) memory. The architecture code may also define stride-efficient memories for implementing convolution. The algorithmic code may include configuration instructions for running the DNN's layers at the processor cores. The algorithmic code may also include a schedule for executing the configuration instructions on the processor cores, for moving network parameters to the processor cores, and for transferring outputs between the layers.

公开(公告)号：US11023360B2

公开(公告)日：2021-06-01

申请号：US16270082

申请日：2019-02-07

Applicant: The MathWorks, Inc.

Inventor： Yongfeng Gu ,  Girish Venkataramani ,  Wang Chen ,  Bharathi Yogaraj ,  Yuteng Zhou ,  Vibha Patil ,  Anusha Vasantala ,  Purshottam Vishwakarma

IPC: G06F11/36 ,  G06F8/41 ,  G06F5/06 ,  G06N7/00 ,  G06F15/78 ,  G06N3/063

Abstract: Systems and methods may configure a programmable logic device to efficiently run a deep learning (DL) network. Architecture code and algorithmic code may be generated. The architecture code may define convolutional and fully connected processor cores structured to run the layers of a Deep Neural Network (DNN). The processor cores may be interconnected by a First In First Out (FIFO) memory. The architecture code may also define stride-efficient memories for implementing convolution. The algorithmic code may include configuration instructions for running the DNN's layers at the processor cores. The algorithmic code may also include a schedule for executing the configuration instructions on the processor cores, for moving network parameters to the processor cores, and for transferring outputs between the layers.

公开(公告)号：US10114917B1

公开(公告)日：2018-10-30

申请号：US15225193

申请日：2016-08-01

Applicant: The MathWorks, Inc.

Inventor： Girish Venkataramani ,  Purshottam Vishwakarma ,  Rama Kokku

IPC: G06F17/50

Abstract: Systems and methods automatically generate code from an executable model. The code may be generated from one or more in-memory representations constructed for the model. The in-memory representations may be analyzed, and portions that can be mapped to DSP slices of a programmable logic device may be identified. The portions may be modified based on information for a particular programmable logic device, such as the structure of the device's DSP slices. The modifications may ensure that elements of the generated code get mapped to DSP slices, when the generated code is used to synthesize the programmable logic device.