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1.发明申请公开(公告)号：US20200151088A1
公开(公告)日：2020-05-14
申请号：US16270082
申请日：2019-02-07
Applicant: The MathWorks, Inc.
Inventor： Yongfeng Gu , Girish Venkataramani , Wang Chen , Bharathi Yogaraj , Yuteng Zhou , Vibha Patil , Anusha Vasantala , Purshottam Vishwakarma
Abstract: Systems and methods may configure a programmable logic device to efficiently run a deep learning (DL) network. Architecture code and algorithmic code may be generated. The architecture code may define convolutional and fully connected processor cores structured to run the layers of a Deep Neural Network (DNN). The processor cores may be interconnected by a First In First Out (FIFO) memory. The architecture code may also define stride-efficient memories for implementing convolution. The algorithmic code may include configuration instructions for running the DNN's layers at the processor cores. The algorithmic code may also include a schedule for executing the configuration instructions on the processor cores, for moving network parameters to the processor cores, and for transferring outputs between the layers.
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Patent Agency Ranking
2.发明授权公开(公告)号：US11023360B2
公开(公告)日：2021-06-01
申请号：US16270082
申请日：2019-02-07
Applicant: The MathWorks, Inc.
Inventor： Yongfeng Gu , Girish Venkataramani , Wang Chen , Bharathi Yogaraj , Yuteng Zhou , Vibha Patil , Anusha Vasantala , Purshottam Vishwakarma
Abstract: Systems and methods may configure a programmable logic device to efficiently run a deep learning (DL) network. Architecture code and algorithmic code may be generated. The architecture code may define convolutional and fully connected processor cores structured to run the layers of a Deep Neural Network (DNN). The processor cores may be interconnected by a First In First Out (FIFO) memory. The architecture code may also define stride-efficient memories for implementing convolution. The algorithmic code may include configuration instructions for running the DNN's layers at the processor cores. The algorithmic code may also include a schedule for executing the configuration instructions on the processor cores, for moving network parameters to the processor cores, and for transferring outputs between the layers.
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公开(公告)号：US10387584B1
公开(公告)日：2019-08-20
申请号：US14559566
申请日：2014-12-03
Applicant: The MathWorks, Inc.
Inventor： Katalin Maria Popovici , Rajiv Ghosh-Roy , Senthilkumar Manickavasagam , Wang Chen , Girish Venkataramani , Wei Zang , Abhijeet H. Gadkari , Matthew H. Fornero
Abstract: A method may include receiving functional model information regarding a set of functional blocks associated with a functional model. The functional model may include a streaming algorithm for exchanging streaming data. The method may include receiving architectural model information regarding physical devices included in a target device from a hardware-software co-design platform. The physical devices may include a software based processing device and a hardware based processing device. The method may include mapping the functional blocks to the physical devices to allow the streaming data to be communicated between the software based processing device and the hardware based processing device. The method may include generating a streaming interface to model communication of the streaming data between the software based processing device and the hardware based processing device. The method may include generating computer code for implementing the functional model on the target device and outputting the computer code.
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4.发明授权公开(公告)号：US09454627B1
公开(公告)日：2016-09-27
申请号：US14640543
申请日：2015-03-06
Applicant: The MathWorks, Inc.
Inventor： Girish Venkataramani , Kiran K. Kintali , Wei Zang , Wang Chen
IPC: G06F17/50
CPC classification number: G06F17/505 , G06F17/5022
Abstract: Systems and methods optimize hardware description generated from a graphical model automatically. The system may include an optimizer. The optimizer may add a serializer component and a deserializer component to the model. The serializer component may receive parallel data and may produce serial data. The serializer may introduce one or more idle cycles into the serial data being produced. The deserializer component may receive serial data and may produce parallel data. The serializer and deserializer components may receive and generate control signals. The control signals may include a valid signal for indicating valid data elements of the serial and parallel data, and a start the start signal for indicating the beginning of a new frame or cycle when constructing parallel data from serial data.
Abstract translation: 系统和方法自动优化从图形模型生成的硬件描述。 该系统可以包括优化器。 优化器可以向模型添加一个串行化器组件和一个解串器组件。 串行器组件可以接收并行数据并且可以产生串行数据。 串行器可能会在正在生成的串行数据中引入一个或多个空闲周期。 解串器组件可以接收串行数据并且可以产生并行数据。 串行器和解串器组件可以接收和产生控制信号。 控制信号可以包括用于指示串行和并行数据的有效数据元素的有效信号，以及当从串行数据构建并行数据时开始用于指示新帧或周期的开始的起始信号。
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公开(公告)号：US09256405B1
公开(公告)日：2016-02-09
申请号：US14185510
申请日：2014-02-20
Applicant: The MathWorks, Inc.
Inventor： Sankalp S. Modi , Wang Chen , Zhihong Zhao , Partha Biswas
IPC: G06F9/44
CPC classification number: G06F8/35
Abstract: A device is configured to receive optimization information associated with a model, determine an amount of delay to be inserted into the model, and determine a sampling factor by which a first data rate associated with a signal is to be modified into a second data rate. The device is configured to determine a region of interest, insert an upsampling block that upsamples the signal entering the region of interest based on the sampling factor, and insert a downsampling block, associated with a unit of delay, which downsamples the signal exiting the region of interest based on the sampling factor. The device is configured to convert the unit of delay into a fast delay block, corresponding to the amount of delay, and insert the fast delay block in the region of interest. The device is configured to generate code associated with the model, and provide the code.
Abstract translation: 设备被配置为接收与模型相关联的优化信息，确定要插入模型的延迟量，以及确定与信号相关联的第一数据速率将被修改为第二数据速率的采样因子。 该设备被配置为确定感兴趣的区域，插入基于采样因子对进入感兴趣区域的信号进行上采样的上采样块，并插入与延迟单元相关联的下采样块，其对离开该区域的信号进行下采样 基于抽样因子的兴趣。 该设备被配置为将延迟单元转换成对应于延迟量的快速延迟块，并将快速延迟块插入到感兴趣的区域中。 该设备被配置为生成与模型相关联的代码，并提供代码。
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公开(公告)号：US09846571B1
公开(公告)日：2017-12-19
申请号：US14596443
申请日：2015-01-14
Applicant: The MathWorks, Inc.
Inventor： Girish Venkataramani , Yongfeng Gu , Wang Chen
CPC classification number: G06F8/35 , G06F11/3672
Abstract: A device generates a model associated with a multi-rate system. The multi-rate system includes a system associated with a clock rate and a sample rate, and the clock rate is greater than the sample rate. The device identifies the clock rate of the multi-rate system based on the model, and identifies a portion, of the model, associated with the sample rate. The device applies clock rate pipelining to adjust the sample rate associated with the portion of the model so that the sample rate substantially equals the clock rate, and generates code associated with the model and the applied clock rate pipelining.
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