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    Three-dimensional memory cell structure
    2.
    发明授权
    Three-dimensional memory cell structure 有权

    公开(公告)号：US11723187B2

    公开(公告)日：2023-08-08

    申请号：US17644982

    申请日：2021-12-17

    Applicant: Tokyo Electron Limited

    Inventor： Paul Gutwin ,  Lars Liebmann ,  Daniel Chanemougame

    IPC: H10B12/00 ,  G11C11/402 ,  G11C11/412 ,  H10B10/00

    CPC classification number: H10B12/30 ,  G11C11/4023 ,  G11C11/412 ,  H10B10/12 ,  H10B12/02

    Abstract: In a semiconductor device, a first stack is positioned over substrate and includes a first pair of transistors and a second pair of transistors stacked over the substrate. A second stack is positioned over the substrate and adjacent to the first stack. The second stack includes a third pair of transistors and a fourth pair of transistors stacked over the substrate. A first capacitor is stacked with the first and second stacks. A second capacitor is positioned adjacent to the first capacitor and stacked with the first and second stacks. A first group of the transistors in the first and second stacks is coupled to each other to form a static random-access memory cell. A second group of the transistors in the first and second stacks is coupled to the first and second capacitors to form a first dynamic random-access memory (DRAM) cell and a second DRAM cell.

    Apparatus and method for simultaneous formation of diffusion break, gate cut, and independent N and P gates for 3D transistor devices
    3.
    发明授权
    Apparatus and method for simultaneous formation of diffusion break, gate cut, and independent N and P gates for 3D transistor devices 有权

    公开(公告)号：US11574845B2

    公开(公告)日：2023-02-07

    申请号：US16848638

    申请日：2020-04-14

    Applicant: TOKYO ELECTRON LIMITED

    Inventor： Daniel Chanemougame ,  Lars Liebmann ,  Jeffrey Smith ,  Anton deVilliers

    IPC: H01L21/8238 ,  H01L27/092

    Abstract: A method of manufacturing a 3D semiconductor device, the method including forming a first target structure, the first target structure including at least one upper gate, at least one bottom gate, and a dielectric separation layer disposed between and separating the at least one upper gate and the at least one bottom gate; removing material in a plurality of material removal areas in the first target structure, the plurality of material removal areas including at least one material removal area that extends through the at least one upper gate to a top of the dielectric separation layer; and forming a first contact establishing a first electrical connection to the upper gate and a second contact establishing a second electrical connection to the at least one bottom gate, such that the first contact and second contact are independent of each other.

    Stacked three-dimensional field-effect transistors
    4.
    发明授权
    Stacked three-dimensional field-effect transistors 有权

    公开(公告)号：US11532708B2

    公开(公告)日：2022-12-20

    申请号：US17334422

    申请日：2021-05-28

    Applicant: Tokyo Electron Limited

    Inventor： Lars Liebmann ,  Jeffrey Smith ,  Daniel Chanemougame ,  Paul Gutwin

    IPC: H01L29/10 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

    Abstract: A semiconductor device includes a first field-effect transistor positioned over a substrate, a second field-effect transistor stacked over the first field-effect transistor, a third field-effect transistor stacked over the second field-effect transistor, and a fourth field-effect transistor stacked over the third field-effect transistor. A bottom gate structure is disposed around a first channel structure of the first field-effect transistor and positioned over the substrate. An intermediate gate structure is disposed over the bottom gate structure and around a second channel structure of the second field-effect transistor and a third channel structure of the third field-effect transistor. A top gate structure is disposed over the intermediate gate structure and around a fourth channel structure of the fourth field-effect transistor. An inter-level contact is formed to bypass the intermediate gate structure from a first side of the intermediate gate structure, and arranged between the bottom gate structure and the top gate structure.

    HIGH DENSITY LOGIC FORMATION USING MULTI-DIMENSIONAL LASER ANNEALING
    6.
    发明申请
    HIGH DENSITY LOGIC FORMATION USING MULTI-DIMENSIONAL LASER ANNEALING 有权

    公开(公告)号：US20220277957A1

    公开(公告)日：2022-09-01

    申请号：US17632212

    申请日：2020-07-29

    Applicant: Tokyo Electron Limited

    Inventor： H. Jim Fulford ,  Mark I. Gardner ,  Jeffrey Smith ,  Lars Liebmann ,  Daniel Chanemougame

    IPC: H01L21/02

    Abstract: A method of forming transistor devices is described that includes forming a first transistor plane on a substrate, the first transistor plane including at least one layer of epitaxial film adaptable for forming channels of field effect transistors, depositing a first insulator layer on the first transistor plane, depositing a first layer of polycrystalline silicon on the first insulator layer, annealing the first layer of polycrystalline silicon using laser heating. The laser heating increases grain size of the first layer of polycrystalline silicon. The method further includes forming a second transistor plane on the first layer of polycrystalline silicon, the second transistor plane being adaptable for forming channels of field effect transistors, depositing a second insulator layer on the second transistor plane, depositing a second layer of polycrystalline silicon on the second insulator layer, and annealing the second layer of polycrystalline silicon using laser heating.

    High density logic formation using multi-dimensional laser annealing
    7.
    发明授权
    High density logic formation using multi-dimensional laser annealing 有权

    公开(公告)号：US11114346B2

    公开(公告)日：2021-09-07

    申请号：US16705485

    申请日：2019-12-06

    Applicant: Tokyo Electron Limited

    Inventor： H. Jim Fulford ,  Mark I. Gardner ,  Jeffrey Smith ,  Lars Liebmann ,  Daniel Chanemougame

    IPC: H01L21/8238 ,  H01L21/822 ,  H01L21/02 ,  H01L29/786 ,  H01L29/66 ,  H01L27/092

    Abstract: A method of forming transistor devices is described that includes forming a first transistor plane on a substrate, the first transistor plane including at least one layer of epitaxial film adaptable for forming channels of field effect transistors, depositing a first insulator layer on the first transistor plane, depositing a first layer of polycrystalline silicon on the first insulator layer, annealing the first layer of polycrystalline silicon using laser heating. The laser heating increases grain size of the first layer of polycrystalline silicon. The method further includes forming a second transistor plane on the first layer of polycrystalline silicon, the second transistor plane being adaptable for forming channels of field effect transistors, depositing a second insulator layer on the second transistor plane, depositing a second layer of polycrystalline silicon on the second insulator layer, and annealing the second layer of polycrystalline silicon using laser heating.

    COMPACT 3D STACKED-CFET ARCHITECTURE FOR COMPLEX LOGIC CELLS
    8.
    发明申请
    COMPACT 3D STACKED-CFET ARCHITECTURE FOR COMPLEX LOGIC CELLS 审中-公开

    公开(公告)号：US20200381430A1

    公开(公告)日：2020-12-03

    申请号：US16849630

    申请日：2020-04-15

    Applicant: Tokyo Electron Limited

    Inventor： Lars Liebmann ,  Jeffrey Smith ,  Anton deVilliers ,  Daniel Chanemougame

    IPC: H01L27/092 ,  H01L23/528 ,  H01L23/535 ,  H01L29/08 ,  H03K19/21

    Abstract: A 3D IC includes a substrate having a substrate surface, a first stack of semiconductor devices stacked along a thickness direction of the substrate, and a second stack of semiconductor devices stacked along the thickness direction of the substrate and provided adjacent to the first stack in a direction along the substrate surface. Each semiconductor device of the first and second stack includes a gate and a pair of source-drain regions provided on opposite sides of the respective gate, and each gate of the first and second stack is a split gate. A gate contact is physically connected to a first split gate of a first one of the semiconductor devices. The gate contact forms at least part of a local interconnect structure that electrically connects the first semiconductor device to a second semiconductor device in the 3D IC.

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