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    METHOD FOR FILLING RECESSED FEATURES IN SEMICONDUCTOR DEVICES WITH A LOW-RESISTIVITY METAL
    1.
    发明申请
    METHOD FOR FILLING RECESSED FEATURES IN SEMICONDUCTOR DEVICES WITH A LOW-RESISTIVITY METAL 有权

    公开(公告)号：US20210287936A1

    公开(公告)日：2021-09-16

    申请号：US17334389

    申请日：2021-05-28

    Applicant: Tokyo Electron Limited

    Inventor： Kai-Hung Yu ,  David O'Meara ,  Nicholas Joy ,  Gyanaranjan Pattanaik ,  Robert Clark ,  Kandabara Tapily ,  Takahiro Hakamata ,  Cory Wajda ,  Gerrit Leusink

    IPC: H01L21/768

    Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.

    Protection Layer Formation during Plasma Etching Conductive Materials
    3.
    发明申请
    Protection Layer Formation during Plasma Etching Conductive Materials 有权

    公开(公告)号：US20240371655A1

    公开(公告)日：2024-11-07

    申请号：US18312427

    申请日：2023-05-04

    Applicant: Tokyo Electron Limited

    Inventor： Yen-Tien Lu ,  Shihsheng Chang ,  Nicholas Joy

    IPC: H01L21/3213 ,  H01L21/02 ,  H01L21/033 ,  H01L21/56

    Abstract: A method of processing a substrate that includes: forming a patterned hardmask layer over a conductive layer to be etched, the conductive layer disposed over a substrate; and patterning the conductive layer using the patterned hardmask layer as an etch mask, by performing a cyclic plasma etch process to gradually form a recess in the conductive layer, each cycle of the cyclic plasma etch process including exposing the substrate to a first plasma including a halogen to etch the conductive layer, and exposing the substrate to a second plasma including a silicon-containing precursor to deposit a silicon-containing protective layer over a top surface of the patterned hardmask layer.

    Method for filling recessed features in semiconductor devices with a low-resistivity metal
    4.
    发明授权
    Method for filling recessed features in semiconductor devices with a low-resistivity metal 有权

    公开(公告)号：US11024535B2

    公开(公告)日：2021-06-01

    申请号：US16598772

    申请日：2019-10-10

    Applicant: Tokyo Electron Limited

    Inventor： Kai-Hung Yu ,  David O'Meara ,  Nicholas Joy ,  Gyanaranjan Pattanaik ,  Robert Clark ,  Kandabara Tapily ,  Takahiro Hakamata ,  Cory Wajda ,  Gerrit Leusink

    IPC: H01L21/768

    Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.

    Method of integrated circuit fabrication with dual metal power rail
    6.
    发明授权
    Method of integrated circuit fabrication with dual metal power rail 有权

    公开(公告)号：US10580691B2

    公开(公告)日：2020-03-03

    申请号：US16001695

    申请日：2018-06-06

    Applicant: Tokyo Electron Limited

    Inventor： Soo Doo Chae ,  Kaoru Maekawa ,  Jeffrey Smith ,  Nicholas Joy ,  Gerrit J. Leusink ,  Kai-Hung Yu

    IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532

    Abstract: A substrate processing method is provided for metal filling of recessed features in a substrate. According to one embodiment, the method includes providing a substrate containing horizontally spaced nested and isolated recessed features, filling the nested and isolated recessed features with a blocking material, and performing in any order: a) sequentially first, removing the blocking material from the nested recessed features, and second, filling the nested recessed features with a first metal, and b) sequentially first, removing the blocking material from the isolated recessed features, and second, filling the isolated recessed features with a second metal that is different from the first metal. According to one embodiment, the first metal may include Ru metal and the second metal may include Cu metal. According to one embodiment, a microelectronic device containing metal filled recessed features is provided.

    PLATFORM AND METHOD OF OPERATING FOR INTEGRATED END-TO-END CMP-LESS INTERCONNECT PROCESS
    7.
    发明申请
    PLATFORM AND METHOD OF OPERATING FOR INTEGRATED END-TO-END CMP-LESS INTERCONNECT PROCESS 审中-公开

    公开(公告)号：US20190295887A1

    公开(公告)日：2019-09-26

    申请号：US16356272

    申请日：2019-03-18

    Applicant: Tokyo Electron Limited

    Inventor： Ying Trickett ,  Kai-Hung Yu ,  Nicholas Joy ,  Kaoru Maekawa ,  Robert Clark

    IPC: H01L21/768 ,  H01L21/67 ,  H01L21/677 ,  H01L21/66

    Abstract: A method of processing materials on a semiconductor workpiece using an integrated sequence of processing steps executed on a common manufacturing platform hosting a plurality of processing modules including one or more film-forming modules, one or more etching modules, and one or more transfer modules is provided. A workpiece having an upper planar surface is received into the common manufacturing platform. The method further includes conformally applying a thin film over the feature pattern using one of the film-forming modules, removing the thin film from upper surfaces of the feature pattern using one of the etching modules to leave behind the thin film in the recessed feature, and removing the fill material from the upper planar surface of the workpiece. The integrated sequence of processing steps is executed in a controlled environment within the common manufacturing platform and without leaving the controlled environment.

    Method for selective etching at an interface between materials
    10.
    发明授权
    Method for selective etching at an interface between materials 有权

    公开(公告)号：US11133194B2

    公开(公告)日：2021-09-28

    申请号：US16796675

    申请日：2020-02-20

    Applicant: Tokyo Electron Limited

    Inventor： Sergey Voronin ,  Christopher Catano ,  Nicholas Joy ,  Alok Ranjan ,  Christopher Talone

    IPC: H01L21/02 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/423 ,  H01L29/786

    Abstract: A method of etching a substrate includes generating plasma comprising a first concentration of an etchant and a second concentration of an inhibitor and etching the substrate by exposing an exposed interface between a first material and a second material to the plasma. The first material includes a lower reactivity to both the etchant and the inhibitor than the second material. The first concentration is less than the second concentration. Etching the substrate includes etching the first material and the second material at the exposed interface to form an etched indentation including an enriched region of the second material, forming a passivation layer at the enriched region using the inhibitor, and etching the first material at the etched indentation. The passivation layer reduces an etch rate of the second material to a reduced rate that is less than an etch rate of the first material.

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