公开(公告)号：US20250054809A1

公开(公告)日：2025-02-13

申请号：US18366492

申请日：2023-08-07

Applicant: Tokyo Electron Limited

Inventor： Kandabara Tapily ,  Subhadeep Kal ,  Peng Wang ,  Peter Biolsi

IPC: H01L21/768 ,  H01L21/311

Abstract: A method of processing a substrate that includes: forming a pattern of an electrically conductive layer over the substrate, the electrically conductive layer and a first dielectric layer being exposed at a surface of the substrate; selectively depositing a graphene layer over the electrically conductive layer relative to the first dielectric layer; selectively depositing a second dielectric layer over the first dielectric layer relative to the graphene layer; and depositing a third dielectric layer over the substrate, the third dielectric layer covering the second dielectric layer and the graphene layer.

公开(公告)号：US11557479B2

公开(公告)日：2023-01-17

申请号：US16824346

申请日：2020-03-19

Applicant: Tokyo Electron Limited

Inventor： Eric Chih-Fang Liu ,  Akiteru Ko ,  Subhadeep Kal ,  Toshiharu Wada

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/027

Abstract: Methods process microelectronic workpieces with inverse extreme ultraviolet (EUV) patterning processes. In part, the inverse patterning techniques are applied to reduce or eliminate defects experienced with conventional EUV patterning processes. The inverse patterning techniques include additional process steps as compared to the conventional EUV patterning processes, such as an overcoat process, an etch back or planarization process, and a pattern removal process. In addition, further example embodiments combine inverse patterning techniques with line smoothing treatments to reduce pattern roughness and achieve a target level of line roughness. By using this additional technique, line pattern roughness can be significantly improved in addition to reducing or eliminating microbridge and/or other defects.

公开(公告)号：US10991626B2

公开(公告)日：2021-04-27

申请号：US16898014

申请日：2020-06-10

Applicant: Tokyo Electron Limited

Inventor： Jeffrey Smith ,  Subhadeep Kal ,  Anton Devilliers

IPC: H01L21/822 ,  H01L21/8238 ,  H01L29/423 ,  H01L21/308 ,  H01L21/306 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/10 ,  H01L29/786 ,  H01L27/06

Abstract: A semiconductor device includes: a substrate having a planar surface; a first gate-all-around field effect transistor (GAA-FET) provided on said substrate and comprising a first channel having an untrimmed volume of first channel material corresponding to a volume of the first channel material within a first stacked fin structure from which the first channel was formed; and a second GAA-FET provided on said substrate and comprising a second channel having a trimmed volume of second channel material which is less than said untrimmed volume of first channel material by a predetermined trim amount corresponding to a delay adjustment of the second GAA-FET relative to the first GAA-FET, wherein said first and second GAA FETs are electrically connected as complementary FETs.

公开(公告)号：US20210020454A1

公开(公告)日：2021-01-21

申请号：US16890141

申请日：2020-06-02

Applicant: Tokyo Electron Limited

Inventor： Subhadeep Kal ,  Daisuke Ito ,  Matthew Flaugh ,  Yusuke Muraki ,  Aelan Mosden

IPC: H01L21/3213 ,  C23F1/02 ,  C23F1/12

Abstract: A method for the dry removal of a material on a microelectronic workpiece is described. The method includes receiving a substrate having a working surface exposing a metal layer and having at least one other material exposed or underneath the metal layer; and differentially etching the metal layer relative to the other material by exposing the substrate to a controlled gas-phase environment containing an anhydrous halogen compound.

公开(公告)号：US10580660B2

公开(公告)日：2020-03-03

申请号：US15191963

申请日：2016-06-24

Applicant: Tokyo Electron Limited

Inventor： Subhadeep Kal ,  Nihar Mohanty ,  Angelique D. Raley ,  Aelan Mosden ,  Scott W. Lefevre

IPC: H01L21/311 ,  H01L21/67

Abstract: A method and system for the dry removal of a material on a microelectronic workpiece are described. The method includes receiving a workpiece having a surface exposing a target layer to be at least partially removed, placing the workpiece on a workpiece holder in a dry, non-plasma etch chamber, and selectively removing at least a portion of the target layer from the workpiece. The selective removal includes operating the dry, non-plasma etch chamber to perform the following: exposing the surface of the workpiece to a chemical environment at a first setpoint temperature in the range of 35 degrees C. to 100 degrees C. to chemically alter a surface region of the target layer, and then, elevating the temperature of the workpiece to a second setpoint temperature at or above 100 degrees C. to remove the chemically treated surface region of the target layer.

公开(公告)号：US09997598B2

公开(公告)日：2018-06-12

申请号：US15671771

申请日：2017-08-08

Applicant: TOKYO ELECTRON LIMITED

Inventor： Jeffrey Smith ,  Anton deVilliers ,  Nihar Mohanty ,  Subhadeep Kal ,  Kandabara Tapily

IPC: H01L29/06 ,  H01L29/423 ,  H01L27/11 ,  H01L21/8238

CPC classification number: H01L29/0676 ,  H01L21/823807 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1104 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: A semiconductor device including a substrate and a gate region of a field effect transistor formed on the substrate. The gate region includes vertically stacked nanowires having longitudinal axes that extend parallel with a working surface of the substrate. A given stack of vertically stacked nanowires includes at least two nanowires vertically aligned in which a p-type nanowire and an n-type nanowire are spatially separated from each other vertically. The semiconductor device further includes a step-shaped connecting structure formed within the gate region that electrically connects each nanowire to positions above the gate region. A first gate electrode has a step-shaped profile and connects to a first-level nanowire.

公开(公告)号：US09984890B2

公开(公告)日：2018-05-29

申请号：US15448334

申请日：2017-03-02

Applicant: Tokyo Electron Limited

Inventor： Subhadeep Kal ,  Kandabara N. Tapily ,  Aelan Mosden

IPC: H01L21/3065 ,  H01L21/322 ,  H01L21/306 ,  H01J37/32 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/3065 ,  H01J37/32357 ,  H01J37/32724 ,  H01L21/0234 ,  H01L21/30604 ,  H01L21/31116 ,  H01L21/32135 ,  H01L21/322 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775

Abstract: Isotropic silicon and silicon-germanium etching with tunable selectivity is described. The method includes receiving a substrate having a layer of silicon and a layer of silicon-germanium with sidewall surfaces of silicon and silicon-germanium being uncovered, positioning the substrate in a processing chamber configured for etching substrates, and modifying uncovered surfaces of silicon and silicon-germanium by exposing the uncovered surfaces of silicon and silicon-germanium to radical species. The method further includes executing a gaseous chemical oxide removal process that includes flowing a mixture of a nitrogen-containing gas and a fluorine-containing gas at a first substrate temperature to form a fluorine byproduct followed by executing a sublimation process to remove the fluorine byproduct at a second substrate temperature that is higher than the first substrate temperature, and controlling the second substrate temperature to tune the sublimation rate and etch selectivity of a silicon oxide material relative to a silicon-germanium oxide material.

公开(公告)号：US20170207103A1

公开(公告)日：2017-07-20

申请号：US15405977

申请日：2017-01-13

Applicant: Tokyo Electron Limited

Inventor： Subhadeep Kal ,  Elliott Franke ,  Akiteru Ko ,  Aelan Mosden

IPC: H01L21/3213 ,  H01L21/321

CPC classification number: H01L21/32135 ,  H01L21/0337 ,  H01L21/67109

Abstract: A method for the dry removal of a material on a microelectronic workpiece is described. The method includes receiving a workpiece having a surface exposing a target layer composed of silicon selected from the group consisting of amorphous silicon (a-Si), polycrystalline silicon (poly-Si), and doped silicon that fills a trench or via within a retention layer, and selectively removing at least a portion of the target layer from the retention layer. The selective removal includes exposing the surface of the workpiece to a chemical environment containing N, H, and F at a first setpoint temperature to chemically alter a surface region of the target layer, and then, elevating the temperature of the workpiece to a second setpoint temperature to remove the chemically treated surface region of the target layer.

公开(公告)号：US20240055270A1

公开(公告)日：2024-02-15

申请号：US17886289

申请日：2022-08-11

Applicant: TOKYO ELECTRON LIMITED

Inventor： Ivo Otto, IV ,  Subhadeep Kal

IPC: H01L21/311 ,  H01L21/02 ,  H01J37/32

CPC classification number: H01L21/31116 ,  H01L21/0234 ,  H01J37/32422

Abstract: An etch and surface modification is performed in a plasma, in which ions have been removed so that radicals of the plasma form a modified surface of a layer of substrate. A gas chemistry is reacted with the modified surface to form a reacted modified surface, and the reacted modified surface is removed.

公开(公告)号：US11715643B2

公开(公告)日：2023-08-01

申请号：US16890141

申请日：2020-06-02

Applicant: Tokyo Electron Limited

Inventor： Subhadeep Kal ,  Daisuke Ito ,  Matthew Flaugh ,  Yusuke Muraki ,  Aelan Mosden

IPC: H01L21/3213 ,  C23F1/12 ,  C23F1/02 ,  H01L21/66 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L21/32135 ,  C23F1/02 ,  C23F1/12 ,  H01L21/30621 ,  H01L21/32136 ,  H01L21/32138 ,  H01L22/12 ,  H01L21/0228

Abstract: A method for the dry removal of a material on a microelectronic workpiece is described. The method includes receiving a substrate having a working surface exposing a metal layer and having at least one other material exposed or underneath the metal layer; and differentially etching the metal layer relative to the other material by exposing the substrate to a controlled gas-phase environment containing an anhydrous halogen compound.