公开(公告)号：US20190318916A1

公开(公告)日：2019-10-17

申请号：US16377522

申请日：2019-04-08

Applicant: Tokyo Electron Limited ,  MKS Instruments, Inc.

Inventor： Yusuke Yoshida ,  Sergey Voronin ,  Alok Ranjan ,  David J. Coumou ,  Scott E. White

IPC: H01J37/32

Abstract: Plasma ion energy distribution for ions having different masses is controlled by controlling the relationship between a base RF frequency and a harmonic RF frequency. By the controlling the RF power frequencies, characteristics of the plasma process may be changed based on ion mass. The ions that dominate etching may be selectively based upon whether an ion is lighter or heavier than other ions. Similarly, atomic layer etch processes may be controlled such that the process may be switched between a layer modification step and a layer etch step though adjustment of the RF frequencies. Such switching is capable of being performed within the same gas phase of the plasma process. The control of the RF power includes controlling the phase difference and/or amplitude ratios between a base RF frequency and a harmonic frequency based upon the detection of one or more electrical characteristics within the plasma apparatus.

公开(公告)号：US20190318913A1

公开(公告)日：2019-10-17

申请号：US16377501

申请日：2019-04-08

Applicant: Tokyo Electron Limited ,  MKS Instruments, Inc.

Inventor： Yusuke Yoshida ,  Sergey Voronin ,  Alok Ranjan ,  David J. Coumou ,  Scott E. White

IPC: H01J37/32 ,  H01J37/08

Abstract: Multiple harmonic frequency components are used for plasma excitation in a plasma process. Relative amplitude and/or phase shift between the different frequency components is controlled so as to provide desired ion energy plasma properties. The relative amplitude and/or phase shift may be controlled without direct and/or manual ion energy measurements. Rather, the ion energy within the plasma may be dynamically controlled by monitoring one or more electrical characteristics within the plasma apparatus, such as for example, impedance levels, electrical signals in the radio frequency (RF) generator, electrical signals in a the matching networks, and electrical signals in other circuits of the plasma processing apparatus. The monitoring and control of the ion energy may be accomplished dynamically during the plasma process so as to maintain a desired ion energy distribution.

公开(公告)号：US10818502B2

公开(公告)日：2020-10-27

申请号：US15818273

申请日：2017-11-20

Applicant: TOKYO ELECTRON LIMITED

Inventor： Sergey Voronin ,  Jason Marion ,  Yusuke Yoshida ,  Alok Ranjan ,  Takashi Enomoto ,  Yoshio Ishikawa

IPC: H01L21/3065 ,  H01J37/32 ,  H01L21/67 ,  H01L21/683

Abstract: Systems and methods are disclosed for plasma discharge ignition to reduce surface particles and thereby decrease defects introduced during plasma processing. A microelectronic workpiece is positioned on a holder within a process chamber that includes a first radio frequency (RF) power source configured to couple RF power to a top portion of the process chamber, a second RF power source configured to couple RF power to the holder, and a direct current (DC) power supply. Initially, a process gas for plasma process is flowed into the process chamber. The process gas is ignited to form plasma by activating the second RF power source to apply RF power to the holder. Subsequently, the microelectronic workpiece is clamped to the holder by applying the positive voltage to the holder with the DC power supply, and the first RF power source is activated to maintain the plasma within the process chamber.

公开(公告)号：US20180144946A1

公开(公告)日：2018-05-24

申请号：US15818273

申请日：2017-11-20

Applicant: TOKYO ELECTRON LIMITED

Inventor： Sergey Voronin ,  Jason Marion ,  Yusuke Yoshida ,  Alok Ranjan ,  Takashi Enomoto ,  Yoshio Ishikawa

IPC: H01L21/3065 ,  H01L21/683 ,  H01L21/67

Abstract: Systems and methods are disclosed for plasma discharge ignition to reduce surface particles and thereby decrease defects introduced during plasma processing. A microelectronic workpiece is positioned on a holder within a process chamber that includes a first radio frequency (RF) power source configured to couple RF power to a top portion of the process chamber, a second RF power source configured to couple RF power to the holder, and a direct current (DC) power supply. Initially, a process gas for plasma process is flowed into the process chamber. The process gas is ignited to form plasma by activating the second RF power source to apply RF power to the holder. Subsequently, the microelectronic workpiece is clamped to the holder by applying the positive voltage to the holder with the DC power supply, and the first RF power source is activated to maintain the plasma within the process chamber.

公开(公告)号：US11699741B2

公开(公告)日：2023-07-11

申请号：US17336043

申请日：2021-06-01

Applicant: Tokyo Electron Limited

Inventor： Yusuke Yoshida ,  Sergey Voronin ,  Christopher Talone ,  Alok Ranjan

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/06 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/285 ,  H01L21/02 ,  H01L29/786

CPC classification number: H01L29/6656 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/785 ,  H01L21/0228 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/28556 ,  H01L21/31122 ,  H01L21/32135 ,  H01L29/0653 ,  H01L29/78696

Abstract: In an example, a method includes depositing a first sidewall spacer layer over a substrate having a layer stack including alternating layers of a nanosheet and a sacrificial layer, and a dummy gate formed over the layer stack, the first sidewall spacer layer formed over the dummy gate. The method includes depositing a metal-containing liner over the first sidewall spacer layer; forming a first sidewall spacer along the dummy gate by anisotropically etching the metal-containing liner and the first sidewall spacer layer; performing an anisotropic etch back process to form a plurality of vertical recesses in the layer stack; laterally etching the layer stack and form a plurality of lateral recesses between adjacent nanosheets; depositing a second sidewall spacer layer to fill the plurality of lateral recesses; and etching a portion of the second sidewall spacer layer to expose tips of the nanosheet layers.

公开(公告)号：US10903077B2

公开(公告)日：2021-01-26

申请号：US16511745

申请日：2019-07-15

Applicant: Tokyo Electron Limited

Inventor： Yusuke Yoshida ,  Christopher Catano ,  Christopher Talone ,  Nicholas Joy ,  Sergey Voronin

IPC: H01L21/00 ,  H01L29/00 ,  H01L21/033 ,  H01L29/161 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/66

Abstract: Embodiments are described herein that form silicon germanium nano-wires while reducing or eliminating erosion of nitride layers (e.g., masks and spacers) caused during selective etching of silicon with respect to silicon germanium during formation of silicon germanium nano-wires. oxide layers are used to protect nitride layers during formation of silicon germanium (SiGe) nano-wires. In particular, multilayer spacers including oxide/nitride/oxide layers are formed to protect the nitride layers during selective silicon etch processes that are used to form silicon germanium nano-wires, for example, for field effect transistors (FETs). The multilayer spacers allow for target levels of erosion to be achieved for the nitride layers.

公开(公告)号：US20200273992A1

公开(公告)日：2020-08-27

申请号：US16782680

申请日：2020-02-05

Applicant: Tokyo Electron Limited

Inventor： Sergey Voronin ,  Christopher Catano ,  Sang Cheol Han ,  Shyam Sridhar ,  Yusuke Yoshida ,  Christopher Talone ,  Alok Ranjan

IPC: H01L29/78 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/3065

Abstract: Residue at the base of a feature in a substrate to be etched is limited so that improved profiles may be obtained when forming vertical, narrow pitch, high aspect ratio features, for example fin field effect transistor (FinFET) gates. A thin bottom layer of the feature is formed of a different material than the main layer of the feature. The bottom material may be comprised of a material that preferentially etches and/or preferentially oxidizes as compared to the main layer. The bottom layer may comprise silicon germanium. The preferential etching characteristics may provide a process in which un-etched residuals do not remain. Even if residuals remain, after etch of the feature, an oxidation process may be performed. Enhanced oxidation rates of the bottom material allow any remaining residual to be oxidized. Plasma oxidation may be used. The oxidized material may then be removed by utilizing standard oxide removal mechanisms.

公开(公告)号：US20180323045A1

公开(公告)日：2018-11-08

申请号：US15969472

申请日：2018-05-02

Applicant: Tokyo Electron Limited

Inventor： Jason Marion ,  Yusuke Yoshida ,  Brendan Bathrick ,  Sergey Voronin ,  Alok Ranjan

IPC: H01J37/32 ,  H01L21/67

CPC classification number: H01J37/32834 ,  H01J37/32091 ,  H01J37/32816 ,  H01J2237/0041 ,  H01J2237/334 ,  H01L21/67069 ,  H01L21/6831

Abstract: Manufacturing methods are disclosed to reduce surface particle impurities after a plasma process (e.g., etch, deposition, etc.) by repelling particles trapped within particle wells to reduce surface particle impurities on microelectronic workpieces after termination of the plasma process. Rather than turn off pressure and source power at the termination of the plasma process, the disclosed embodiments first enter a sequence to adjust process parameters to repel particles in a particle well in order to reduce or eliminate the particle well prior to terminating the plasma process. During this particle repel sequence, certain disclosed embodiments adjust parameters to maintain an electrostatic field above the surface of the wafer utilizing low plasma density and ion energy conditions that help to repel particles from the microelectronic workpiece. The disclosed methods allow for the particle well to be exhausted well prior to the collapse of electrostatic forces when the plasma process is terminated.

公开(公告)号：US09412565B2

公开(公告)日：2016-08-09

申请号：US14609554

申请日：2015-01-30

Applicant: Tokyo Electron Limited

Inventor： Yusuke Yoshida ,  Ryou Son ,  Takahiro Senda ,  Masayuki Kohno ,  Naoki Matsumoto

IPC: H01L21/302 ,  H01J37/32 ,  G01J5/00 ,  G01J5/08 ,  G01J5/06

CPC classification number: H01J37/32724 ,  G01J5/0007 ,  G01J5/0044 ,  G01J5/0875 ,  G01J2005/0048 ,  G01J2005/068 ,  H01J37/32522 ,  H01J37/32935 ,  H01J37/3299

Abstract: A temperature measuring method for measuring a temperature of a member corresponding to a measuring object arranged within a chamber of a plasma processing apparatus is provided. The temperature measuring method involves obtaining a function (f) for correcting a correction target temperature (Tmeas) according to a measurement window temperature (Tw), the function (f) being computed based on the correction target temperature (Tmeas) corresponding to a temperature of the measuring object measured via a measurement window arranged at the chamber, a reference temperature (Tobj) corresponding to a temperature of the measuring object measured without using the measurement window, and the measurement window temperature (Tw) corresponding to a temperature of the measurement window. The temperature measuring method further involves measuring the correction target temperature (Tmeas), measuring the measurement window temperature (Tw), and correcting the correction target temperature (Tmeas) according to the measurement window temperature (Tw) based on the obtained function (f).

Abstract translation: 提供了一种用于测量与布置在等离子体处理装置的室内的测量对象相对应的部件的温度的温度测量方法。 温度测量方法包括获得用于根据测量窗口温度（Tw）校正校正目标温度（Tmeas）的功能（f），基于与温度相对应的校正目标温度（Tmeas）计算的函数（f） 通过布置在室中的测量窗测量的测量对象，对应于不使用测量窗口测量的测量对象的温度的参考温度（Tobj）和对应于测量温度的测量窗口温度（Tw） 窗口。 温度测量方法还包括基于所获得的函数（f），根据测量窗口温度（Tw）来测量校正目标温度（Tmeas），测量测量窗口温度（Tw）和校正校正目标温度（Tmeas） 。

公开(公告)号：US20250046617A1

公开(公告)日：2025-02-06

申请号：US18362608

申请日：2023-07-31

Applicant: Tokyo Electron Limited

Inventor： Adam Pranda ,  Yusuke Yoshida ,  Aelan Mosden ,  Yun Han

IPC: H01L21/311 ,  H01J37/32 ,  H01L29/66

Abstract: A method of processing a substrate that includes: forming a bottom passivation layer including an oxide over a first portion of a dielectric layer at a bottom of a recess of the substrate, the recess having sidewalls including a second portion of the dielectric layer; and performing a lateral etch to etch the second portion of the dielectric layer, the bottom passivation layer covering the first portion of the dielectric layer during the lateral etch, and where the forming of the bottom passivation layer includes exposing the substrate to a first plasma including a halogen, and exposing the substrate to a second plasma including oxygen to form the bottom passivation layer.