公开(公告)号：US20240371968A1

公开(公告)日：2024-11-07

申请号：US18774895

申请日：2024-07-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/201 ,  H01L29/40 ,  H01L29/778

Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, a barrier layer on the buffer layer, a gate electrode on the barrier layer, a field plate adjacent to two sides of the gate electrode, and a first passivation layer adjacent to two sides of the gate electrode. Preferably, a sidewall of the field plate includes a first curve.

公开(公告)号：US12080778B2

公开(公告)日：2024-09-03

申请号：US18238534

申请日：2023-08-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/201 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/404 ,  H01L29/778

Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, a barrier layer on the buffer layer, a gate electrode on the barrier layer, a field plate adjacent to two sides of the gate electrode, and a first passivation layer adjacent to two sides of the gate electrode. Preferably, a sidewall of the field plate includes a first curve.

公开(公告)号：US11758824B2

公开(公告)日：2023-09-12

申请号：US17209251

申请日：2021-03-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin

IPC: H10N50/80 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

CPC classification number: H10N50/80 ,  G11C11/161 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, an inter-metal dielectric (IMD) layer on the substrate, a MTJ in the IMD layer on the MTJ region, a first metal interconnection in the IMD layer on the logic region, and protrusions adjacent to two sides of the first metal interconnection. Preferably, the MTJ further includes a bottom electrode, a fixed layer, a barrier layer, a free layer, and a top electrode.

公开(公告)号：US10886395B2

公开(公告)日：2021-01-05

申请号：US16581750

申请日：2019-09-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin

IPC: H01L29/78 ,  H01L29/49 ,  H01L23/535 ,  H01L21/768 ,  H01L29/66 ,  H01L29/20 ,  H01L29/423 ,  H01L29/40 ,  H01L29/739

Abstract: A method for fabricating a tunnel field effect transistor (TFET) includes the steps of providing a substrate and then forming an interfacial layer on the substrate. Preferably, the step of forming the interfacial layer includes the steps of: performing a plasma treatment process to inject a first gas containing nitrogen; injecting a second gas containing oxygen; and injecting a precursor to react with the first gas and the second gas for forming the interfacial layer.

公开(公告)号：US12262645B2

公开(公告)日：2025-03-25

申请号：US18224066

申请日：2023-07-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin

IPC: H10N50/80 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, an inter-metal dielectric (IMD) layer on the substrate, a MTJ in the IMD layer on the MTJ region, a first metal interconnection in the IMD layer on the logic region, and protrusions adjacent to two sides of the first metal interconnection. Preferably, the MTJ further includes a bottom electrode, a fixed layer, a barrier layer, a free layer, and a top electrode.

公开(公告)号：US20220223716A1

公开(公告)日：2022-07-14

申请号：US17705416

申请日：2022-03-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/201 ,  H01L29/40 ,  H01L29/778

Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, a barrier layer on the buffer layer, a gate electrode on the barrier layer, a field plate adjacent to two sides of the gate electrode, and a first passivation layer adjacent to two sides of the gate electrode. Preferably, a sidewall of the field plate includes a first curve.

公开(公告)号：US10991875B2

公开(公告)日：2021-04-27

申请号：US16455674

申请日：2019-06-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22 ,  G11C11/16

Abstract: A semiconductor device includes: a substrate having a magnetic tunneling junction (MTJ) region and a logic region; an inter-metal dielectric (IMD) layer on the substrate; a first metal interconnection in the IMD layer on the logic region; and protrusions adjacent to two sides of the first metal interconnection. Preferably, the first metal interconnection further includes a via conductor and a trench conductor and the protrusions includes a first protrusion on one side of the via conductor and a second protrusion on another side of the via conductor.

公开(公告)号：US20200020792A1

公开(公告)日：2020-01-16

申请号：US16581750

申请日：2019-09-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin

IPC: H01L29/78 ,  H01L29/20 ,  H01L29/66 ,  H01L21/768 ,  H01L23/535 ,  H01L29/49

Abstract: A method for fabricating a tunnel field effect transistor (TFET) includes the steps of providing a substrate and then forming an interfacial layer on the substrate. Preferably, the step of forming the interfacial layer includes the steps of: performing a plasma treatment process to inject a first gas containing nitrogen; injecting a second gas containing oxygen; and injecting a precursor to react with the first gas and the second gas for forming the interfacial layer.

公开(公告)号：US10276443B2

公开(公告)日：2019-04-30

申请号：US15445928

申请日：2017-02-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Chi Chen ,  Chih-Chung Chen ,  An-Chi Liu ,  Chih-Yueh Li ,  Pei-Ching Yeh ,  Tsung-Chieh Yang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/306 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78

Abstract: A method of removing a fin structure includes providing a substrate. A fin structure extends from the substrate. A mask layer is disposed on a top surface of the fin structure. An organic dielectric layer covers the substrate, the fin structure and the mask layer. A first etching process is performed to entirely remove the mask layer by taking the organic dielectric layer as a mask. Then a second etching process is performed to remove the fin structure. The first etching process is preferably an anisotropic etching process, and the second etching process is an isotropic etching process.

公开(公告)号：US20190080968A1

公开(公告)日：2019-03-14

申请号：US15700175

申请日：2017-09-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Yi Wang ,  Tien-Shan Hsu ,  Yu-Chih Su ,  Chi-Hsuan Cheng ,  Cheng-Pu Chiu ,  Te-Chang Hsu ,  Chin-Yang Hsieh ,  An-Chi Liu ,  Kuan-Lin Chen ,  Yao-Jhan Wang

IPC: H01L21/8234 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/762

Abstract: A method of fabricating fins includes providing a silicon substrate. The silicon substrate is etched to form numerous fin elements. A surface of each of the fin elements is silicon. Etch residues are formed on the fin elements after the silicon substrate is etched. After that, a flush step is performed on the fin elements by flushing the surface of each of the fin elements with fluorocarbons. The etch residues on the fin elements are removed by the flush step. After the flush step, a strip step is performed on the fin elements by treating the surface of each of the fin elements with oxygen plasma.