公开(公告)号：US20240128214A1

公开(公告)日：2024-04-18

申请号：US18398204

申请日：2023-12-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Aaron Chen ,  Chi Ren ,  Yi Hsin Liu

IPC: H01L23/00 ,  H01L23/522

CPC classification number: H01L24/05 ,  H01L23/5226 ,  H01L24/03 ,  H01L23/53228 ,  H01L2224/0391 ,  H01L2924/1438 ,  H01L2924/14511

Abstract: An integrated circuit structure includes an aluminum pad layer on a dielectric stack, a passivation layer covering the aluminum pad layer, and an aluminum shield layer including aluminum routing patterns disposed directly above an embedded memory area and embedded in the dielectric stack. The aluminum shield layer is electrically connected to the uppermost copper layer through a plurality of tungsten vias. The plurality of tungsten vias is embedded in the dielectric stack.

公开(公告)号：US20170301683A1

公开(公告)日：2017-10-19

申请号：US15132574

申请日：2016-04-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Aaron Chen ,  Chi Ren

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/423 ,  H01L29/788 ,  H01L29/06

CPC classification number: H01L27/11546 ,  H01L29/42328 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/7881

Abstract: A semiconductor device with split gate flash memory cell structure includes a substrate having a first area and a second area, at least a first cell formed in the first area and at least a second cell formed in the second area. The first cell includes a first dielectric layer formed on the substrate, a floating gate (FG), a word line and an erase gate (EG) formed on the first dielectric layer, an interlayer dielectric (ILD) layer, an inter-gate dielectric layer and a control gate (CG). The FG is positioned between the word line and the EG, and the ILD layer is formed on the word line and the EG, wherein the ILD layer has a trench exposing the FG. The inter-gate dielectric layer is formed in the trench as a liner, and the CG formed in the trench is surrounded by the inter-gate dielectric layer.

公开(公告)号：US20160322372A1

公开(公告)日：2016-11-03

申请号：US14726984

申请日：2015-06-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Qiu-Ji Zhao ,  Ling Wu ,  Wei Meng ,  Zhi-Hui Jiao ,  Zhi-Guo Li ,  Chi Ren

IPC: H01L27/115

CPC classification number: H01L27/11534 ,  H01L21/82345 ,  H01L27/11546 ,  H01L27/11548 ,  H01L27/11573

Abstract: A semiconductor device includes a substrate, a plurality of memory cells, a logic gate electrode and a high-voltage gate electrode. The substrate at least includes a memory area, a high-voltage area and a logic area. The memory cells are disposed in the memory area. The logic gate electrode is disposed on the logic area. The high-voltage gate electrode has a first portion and a second portion in contact with each other and stacked on the high-voltage area. The high-voltage gate electrode has a thickness substantially greater than that of the logic gate electrode.

Abstract translation: 半导体器件包括衬底，多个存储单元，逻辑门电极和高压栅电极。 基板至少包括存储区域，高压区域和逻辑区域。 存储单元被布置在存储器区域中。 逻辑门电极设置在逻辑区域上。 高电压栅电极具有彼此接触并堆叠在高电压区域上的第一部分和第二部分。 高压栅电极的厚度显着大于逻辑栅电极的厚度。

公开(公告)号：US09472562B1

公开(公告)日：2016-10-18

申请号：US14726984

申请日：2015-06-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Qiu-Ji Zhao ,  Ling Wu ,  Wei Meng ,  Zhi-Hui Jiao ,  Zhi-Guo Li ,  Chi Ren

IPC: H01L27/115

CPC classification number: H01L27/11534 ,  H01L21/82345 ,  H01L27/11546 ,  H01L27/11548 ,  H01L27/11573

Abstract: A semiconductor device includes a substrate, a plurality of memory cells, a logic gate electrode and a high-voltage gate electrode. The substrate at least includes a memory area, a high-voltage area and a logic area. The memory cells are disposed in the memory area. The logic gate electrode is disposed on the logic area. The high-voltage gate electrode has a first portion and a second portion in contact with each other and stacked on the high-voltage area. The high-voltage gate electrode has a thickness substantially greater than that of the logic gate electrode.

Abstract translation: 半导体器件包括衬底，多个存储单元，逻辑门电极和高压栅电极。 基板至少包括存储区域，高压区域和逻辑区域。 存储单元被布置在存储器区域中。 逻辑门电极设置在逻辑区域上。 高电压栅电极具有彼此接触并堆叠在高电压区域上的第一部分和第二部分。 高压栅电极的厚度显着大于逻辑栅电极的厚度。

公开(公告)号：US11882699B2

公开(公告)日：2024-01-23

申请号：US17224100

申请日：2021-04-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Zhiguo Li ,  Chi Ren

IPC: H10B43/20 ,  H01L29/78 ,  H01L29/66 ,  H10B41/20

CPC classification number: H10B43/20 ,  H01L29/66795 ,  H01L29/7851 ,  H10B41/20

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell for FinFET includes a fin, a control gate and a selective metal gate. The fin is on a top surface of a substrate, wherein the fin has two sidewalls and a top surface, and the fin includes a memory region and a logic region. The control gate is disposed over the fin of the memory region and covers the two sidewalls and the top surface of the fin, wherein the control gate includes a charge trapping layer and a control electrode, wherein the charge trapping layer is sandwiched by the fin and the control electrode. The selective metal gate is disposed over the fin adjacent to the control gate and covers the two sidewalls and the top surface of the fin. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.

公开(公告)号：US11699730B2

公开(公告)日：2023-07-11

申请号：US17510371

申请日：2021-10-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Zhiguo Li ,  Xiaojuan Gao ,  Chi Ren

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/788

CPC classification number: H01L29/42328 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7883

Abstract: A semiconductor memory device includes a substrate; a source diffusion region in the substrate; a pair of floating gates disposed on opposite of the source diffusion region; a first dielectric cap layer disposed directly on each of the floating gates; an erase gate disposed on the source diffusion region and partially overlapping an upper inner corner of each of the floating gates; a second dielectric cap layer disposed on the erase gate and the first dielectric cap layer; a select gate disposed on a sidewall of the first dielectric cap layer; and a drain diffusion region disposed in the substrate and adjacent to the select gate.

公开(公告)号：US20200373436A1

公开(公告)日：2020-11-26

申请号：US16452311

申请日：2019-06-25

Applicant: United Microelectronics Corp.

Inventor： Liang Yi ,  Zhiguo Li ,  Chi Ren

IPC: H01L29/792 ,  H01L29/788 ,  H01L29/423 ,  H01L29/66

Abstract: A structure of a memory device and a fabrication method thereof are provided. The structure of the memory device includes a tunneling layer disposed on a substrate. A first oxide/nitride/oxide (ONO) layer is disposed on the substrate abutting to the tunneling layer. A floating gate is disposed on the tunneling layer, wherein a side portion of the floating gate is also disposed on the first ONO layer. A second ONO layer is disposed on the floating gate. A control gate is disposed on the second ONO layer. An isolation layer is disposed on first sidewalls of the floating gate and sidewalls of the control gate. An erase gate is disposed on the first ONO layer, wherein the erase gate is isolated from the floating gate and the control gate by the isolation layer.

公开(公告)号：US20150249158A1

公开(公告)日：2015-09-03

申请号：US14194957

申请日：2014-03-03

Applicant: United Microelectronics Corp.

Inventor： Wei Cheng ,  Hua-Kuo Lee ,  Ching-Long Tsai ,  Chi Ren ,  Cheng-Yuan Hsu

IPC: H01L29/788 ,  H01L21/3213 ,  H01L29/40

CPC classification number: H01L29/7883 ,  H01L27/11524 ,  H01L29/42328

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a first gate structure, a second gate electrode, a third gate electrode and a protective layer. The first gate structure comprises a first gate electrode disposed on the substrate and a first gate dielectric covering the first gate electrode. The second gate electrode is disposed on and electrically isolated from the first gate electrode. The first gate structure has an extending portion relative to the second gate electrode. The third gate electrode is disposed adjacent to and electrically isolated from the first gate electrode and the second gate electrode. The third gate has an extending portion between a lower surface of the protective layer and an upper surface of the extending portion of the first gate structure.

Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括衬底，第一栅极结构，第二栅电极，第三栅电极和保护层。 第一栅极结构包括设置在衬底上的第一栅极电极和覆盖第一栅电极的第一栅极电介质。 第二栅电极设置在第一栅电极上并与第一栅极电隔离。 第一栅极结构具有相对于第二栅电极的延伸部分。 第三栅电极设置成与第一栅电极和第二栅电极相邻并与之隔离。 第三栅极在保护层的下表面和第一栅极结构的延伸部分的上表面之间具有延伸部分。

公开(公告)号：US12249658B2

公开(公告)日：2025-03-11

申请号：US18444785

申请日：2024-02-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Sung Huang ,  Chi Ren

IPC: H01L29/792 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66

Abstract: A control gate is formed on the substrate. A source diffusion region is formed in the substrate and on a first side of the control gate. A select gate is formed on the source diffusion region. The select gate has a recessed top surface. A charge storage structure is formed under the control gate. A first spacer is formed between the select gate and the control gate and between the charge storage structure and the select gate. A wordline gate is formed on a second side of the control gate opposite to the select gate. A second spacer is formed between the wordline gate and the control gate. A drain diffusion region is formed in the substrate and adjacent to the wordline gate.

公开(公告)号：US11955565B2

公开(公告)日：2024-04-09

申请号：US17472586

申请日：2021-09-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Sung Huang ,  Chi Ren

IPC: H10B43/30 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L29/792 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/66833

Abstract: A semiconductor memory device includes a substrate; a control gate disposed on the substrate; a source diffusion region disposed in the substrate and on a first side of the control gate; a select gate disposed on the source diffusion region, wherein the select gate has a recessed top surface; a charge storage structure disposed under the control gate; a first spacer disposed between the select gate and the control gate and between the charge storage structure and the select gate; a wordline gate disposed on a second side of the control gate opposite to the select gate; a second spacer between the wordline gate and the control gate; and a drain diffusion region disposed in the substrate and adjacent to the wordline gate.