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公开(公告)号：US20240237554A1
公开(公告)日：2024-07-11
申请号：US18611729
申请日：2024-03-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hung-Chan Lin , Yu-Ping Wang , Chien-Ting Lin
Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spin orbit torque (SOT) layer on the MTJ, a spacer adjacent to the MTJ and the first SOT layer, and a second SOT layer on the first SOT layer. Preferably, the first SOT layer and the second SOT layer are made of same material.
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公开(公告)号：US20240237553A1
公开(公告)日：2024-07-11
申请号：US18611723
申请日：2024-03-21
Applicant: United Microelectronics Corp.
Inventor： Hung-Chan Lin , Yu-Ping Wang , Chien-Ting Lin
Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spin orbit torque (SOT) layer on the MTJ, a second SOT layer on the first SOT layer, a hard mask between the first SOT layer and the second SOT layer, and a spacer adjacent to the MTJ, the first SOT layer, and the hard mask.
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公开(公告)号：US20230097481A1
公开(公告)日：2023-03-30
申请号：US17518571
申请日：2021-11-03
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hung-Chan Lin , Yu-Ping Wang , Chien-Ting Lin
Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a first spin orbit torque (SOT) layer on the MTJ stack; forming a first hard mask on the first SOT layer; and using a second hard mask to pattern the first hard mask, the first SOT layer, and the MTJ stack to form a MTJ.
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公开(公告)号：US20210390993A1
公开(公告)日：2021-12-16
申请号：US17460348
申请日：2021-08-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Yu-Ping Wang , Chen-Yi Weng , Chin-Yang Hsieh , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Jing-Yin Jhang , Chien-Ting Lin
Abstract: A method for forming a semiconductor structure is disclosed. A substrate having a logic device region and a memory device region is provided. A first dielectric layer is formed on the substrate. Plural memory stack structures are formed on the first dielectric layer on the memory device region. An insulating layer is formed and conformally covers the memory stack structures and the first dielectric layer. An etching back process is performed to remove a portion of the insulating layer without exposing any portion of the memory stack structures. After the etching back process, a second dielectric layer is formed on the insulating layer and completely fills the spaces between the memory stack structures.
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公开(公告)号：US20200227625A1
公开(公告)日：2020-07-16
申请号：US16261524
申请日：2019-01-29
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Yi-Wei Tseng , Meng-Jun Wang , Chen-Yi Weng , Chin-Yang Hsieh , Jing-Yin Jhang , Yu-Ping Wang , Chien-Ting Lin , Ying-Cheng Liu , Yi-An Shih , Yi-Hui Lee , I-Ming Tseng
Abstract: A magneto-resistive random access memory (MRAM) cell includes a substrate having a dielectric layer disposed thereon, a conductive via disposed in the dielectric layer, and a cylindrical stack disposed on the conductive via. The cylindrical stack includes a bottom electrode, a magnetic tunneling junction (MTJ) layer on the bottom electrode, and a top electrode on the MTJ layer. A spacer layer is disposed on a sidewall of the cylindrical stack. The top electrode protrudes from a top surface of the spacer layer.
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Patent Agency Ranking
公开(公告)号：US10062770B2
公开(公告)日：2018-08-28
申请号：US15335418
申请日：2016-10-26
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chien-Ting Lin , Shih-Hung Tsai
IPC: H01L29/06 , H01L29/08 , H01L29/66 , H01L29/78 , H01L27/092 , H01L21/762 , H01L21/8238 , H01L21/84 , H01L27/12
CPC classification number: H01L29/66598 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823878 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/0653 , H01L29/0847 , H01L29/66636 , H01L29/66795 , H01L29/7833 , H01L29/7851
Abstract: A complementary metal oxide semiconductor field-effect transistor (MOSFET) includes a substrate, a first MOSFET and a second MOSFET. The first MOSFET is disposed on the substrate within a first transistor region and the second MOSFET is disposed on the substrate within a second transistor region. The first MOSFET includes a first fin structure, two first lightly-doped regions, two first doped regions and a first gate structure. The first fin structure includes a first body portion and two first epitaxial portions, wherein each of the first epitaxial portions is disposed on each side of the first body portion. A first vertical interface is between the first body portion and each of the first epitaxial portions so that the first-lightly doped region is able to be uniformly distributed on an entire surface of each first vertical interface.
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公开(公告)号：US20170069543A1
公开(公告)日：2017-03-09
申请号：US14884746
申请日：2015-10-15
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ching-Yu Chang , Li-Wei Feng , Shih-Hung Tsai , Ssu-I Fu , Jyh-Shyang Jenq , Chien-Ting Lin , Yi-Ren Chen , Shou-Wei Hsieh , Hsin-Yu Chen , Chun-Hao Lin
IPC: H01L21/8238 , H01L21/324
CPC classification number: H01L21/823821 , H01L21/02129 , H01L21/324 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/823878
Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon and a shallow trench isolation (STI) around the fin-shaped structure, in which the fin-shaped structure has a top portion and a bottom portion; forming a first doped layer on the STI and the top portion; and performing a first anneal process.
Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有鳍状结构的衬底和围绕鳍状结构的浅沟槽隔离（STI），其中鳍状结构具有顶部和底部; 在STI和顶部上形成第一掺杂层; 并执行第一退火处理。
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公开(公告)号：US20170047422A1
公开(公告)日：2017-02-16
申请号：US14855357
申请日：2015-09-15
Applicant: United Microelectronics Corp.
Inventor： Chien-Ting Lin , Shih-Fang Tzou
IPC: H01L29/66 , H01L23/535 , H01L21/768 , H01L29/78
CPC classification number: H01L29/6656 , H01L21/76897 , H01L23/535 , H01L29/41791 , H01L29/66545 , H01L29/66795 , H01L29/785
Abstract: A semiconductor device includes a substrate, gate electrodes, spacers and contact structures. The gate electrodes are disposed on the substrate, and the spacers are disposed on the sidewalls of the gate electrodes. Each of the spacers has an inner sidewall and an outer sidewall. The contact structure is disposed between the gate electrodes, and its bottom is in direct contact with all the region of the outer sidewall of the spacers.
Abstract translation: 半导体器件包括衬底，栅电极，间隔物和接触结构。 栅电极设置在衬底上，并且间隔物设置在栅电极的侧壁上。 每个间隔件具有内侧壁和外侧壁。 接触结构设置在栅电极之间，其底部与间隔物的外侧壁的所有区域直接接触。
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9.发明授权Complementary metal oxide semiconductor field effect transistor, metal oxide semiconductor field effect transistor and manufacturing method thereof 有权互补金属氧化物半导体场效应晶体管，金属氧化物半导体场效应晶体管及其制造方法公开(公告)号：US09536792B2
公开(公告)日：2017-01-03
申请号：US13738934
申请日：2013-01-10
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chien-Ting Lin , Shih-Hung Tsai
IPC: H01L29/66 , H01L29/78 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L27/12
CPC classification number: H01L29/66598 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823878 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/0653 , H01L29/0847 , H01L29/66636 , H01L29/66795 , H01L29/7833 , H01L29/7851
Abstract: A complementary metal oxide semiconductor field-effect transistor (MOSFET) includes a substrate, a first MOSFET and a second MOSFET. The first MOSFET is disposed on the substrate within a first transistor region and the second MOSFET is disposed on the substrate within a second transistor region. The first MOSFET includes a first fin structure, two first lightly-doped regions, two first doped regions and a first gate structure. The first fin structure includes a first body portion and two first epitaxial portions, wherein each of the first epitaxial portions is disposed on each side of the first body portion. A first vertical interface is between the first body portion and each of the first epitaxial portions so that the first-lightly doped region is able to be uniformly distributed on an entire surface of each first vertical interface.
Abstract translation: 互补金属氧化物半导体场效应晶体管（MOSFET）包括衬底，第一MOSFET和第二MOSFET。 第一MOSFET设置在第一晶体管区域内的衬底上，并且第二MOSFET设置在第二晶体管区域内的衬底上。 第一MOSFET包括第一鳍结构，两个第一轻掺杂区，两个第一掺杂区和第一栅结构。 第一翅片结构包括第一主体部分和两个第一外延部分，其中每个第一外延部分设置在第一主体部分的每一侧上。 第一垂直接口位于第一主体部分和第一外延部分之间，使得第一轻掺杂区域能够均匀分布在每个第一垂直界面的整个表面上。
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公开(公告)号：US09530862B2
公开(公告)日：2016-12-27
申请号：US14811814
申请日：2015-07-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Po-Chao Tsao , Chien-Ting Lin , Chien-Ming Lai , Chi-Mao Hsu
IPC: H01L21/4763 , H01L29/66 , H01L21/28 , H01L21/321 , H01L29/78 , H01L29/423 , H01L29/51 , H01L27/092 , H01L29/49 , H01L21/8238
CPC classification number: H01L29/66545 , H01L21/28088 , H01L21/28185 , H01L21/32115 , H01L21/823842 , H01L27/0922 , H01L29/42364 , H01L29/42376 , H01L29/4966 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/78 , H01L29/7833
Abstract: A manufacturing method of semiconductor devices having metal gate includes following steps. A substrate having a first semiconductor device and a second semiconductor device formed thereon is provided. The first semiconductor device includes a first gate trench and the second semiconductor device includes a second gate trench. A first work function metal layer is formed in the first gate trench and the second gate trench. A portion of the first work function metal layer is removed from the second gate trench. A second work function metal layer is formed in the first gate trench and the second gate trench. The second work function metal layer and the first work function metal layer include the same metal material. A third work function metal layer and a gap-filling metal layer are sequentially formed in the first gate trench and the second gate trench.
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