公开(公告)号：US20240313046A1

公开(公告)日：2024-09-19

申请号：US18134555

申请日：2023-04-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Guang-Yu Lo ,  Chun-Tsen Lu ,  Chung-Fu Chang ,  Chih-Shan Wu ,  Yu-Hsiang Lin ,  Wei-Hao Chang

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method for fabricating a semiconductor device includes the steps of forming a fin-shaped structure on a substrate, forming a first trench and a second trench in the fin-shaped structure, forming a first dielectric layer in the first trench and the second trench, removing part of the first dielectric layer, forming a second dielectric layer in the first trench and the second trench to form a first single diffusion break (SDB) structure and a second SDB structure, and then forming a gate structure on the fin-shaped structure, the first SDB structure, and the second SDB structure.

公开(公告)号：US09589970B1

公开(公告)日：2017-03-07

申请号：US15225842

申请日：2016-08-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yuan-Heng Tseng ,  Chih-Shan Wu

IPC: H01L27/112 ,  H01L29/423 ,  H01L29/778 ,  H01L29/78 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L27/092 ,  H01L29/06 ,  H01L23/525

CPC classification number: H01L27/11206 ,  H01L23/5252 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/7848 ,  H01L29/785

Abstract: An antifuse one-time programmable (OTP) memory cell includes a semiconductor substrate, an isolation region, and a fin structure protruding from a top surface of the isolation region. The fin structure has an end portion with a sidewall surface above the top surface. A select gate transistor is disposed on the fin structure. The select gate transistor has a select gate traversing the fin structure, a select gate dielectric layer, a drain region, and a source region. A vertical program gate transistor is serially connected to the select gate transistor through the source region. The vertical program gate transistor has a program gate directly disposed on the isolation region and covering the sidewall surface of the end portion, and a program gate dielectric layer between the program gate and the sidewall surface.

Abstract translation: 反熔丝一次可编程（OTP）存储单元包括从隔离区的顶表面突出的半导体衬底，隔离区和鳍结构。 翅片结构具有在顶表面上方具有侧壁表面的端部。 选择栅晶体管设置在鳍结构上。 选择栅极晶体管具有穿过鳍状结构的选择栅极，选择栅极电介质层，漏极区域和源极区域。 垂直编程门晶体管通过源极区域与选择栅极晶体管串联连接。 垂直程序栅极晶体管具有直接设置在隔离区上并覆盖端部侧壁表面的程序栅极和程序栅极与侧壁表面之间的程序栅极介电层。