公开(公告)号：US20200013783A1

公开(公告)日：2020-01-09

申请号：US16571202

申请日：2019-09-16

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang ,  Sho-Shen Lee

IPC: H01L27/108 ,  G11C11/401

Abstract: The present invention provides a method for forming a dynamic random access memory (DRAM) structure, the method including: firstly, a substrate is provided, a cell region and a peripheral region are defined on the substrate, a plurality of buried word lines is then formed in the cell region of the substrate, next, a shallow trench isolation structure is formed in the peripheral region adjacent to the cell region, wherein a concave top surface is formed on the shallow trench isolation structure, afterwards, a first dummy bit line gate is formed within the shallow trench isolation structure of the peripheral area, and a second dummy bit line gate is formed in the cell region and adjacent to the first dummy bit line gate, wherein a top surface of the first dummy bit line gate is lower than a top surface of the second dummy bit line gate.

公开(公告)号：US09875928B2

公开(公告)日：2018-01-23

申请号：US14682124

申请日：2015-04-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/53295

Abstract: A method for fabricating metal interconnect structure is disclosed. The method includes the steps of: providing a substrate having a first inter-metal dielectric (IMD) layer thereon; forming a metal interconnection in the first IMD layer; removing part of the first IMD layer; forming a spacer adjacent to the metal interconnection; and using the spacer as mask to remove part of the first IMD layer for forming an opening in the first IMD layer.

公开(公告)号：US20170309520A1

公开(公告)日：2017-10-26

申请号：US15158608

申请日：2016-05-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Kuan-Ying Lai

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L21/823456 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a first metal gate and a second metal gate are formed on the substrate, in which the first metal gate includes a first work function metal layer, the second metal gate includes a second work function metal layer, the first metal gate and the second metal gate include different size, and the first work function metal layer and the second work function metal layer include different thickness.

公开(公告)号：US20170053980A1

公开(公告)日：2017-02-23

申请号：US14830756

申请日：2015-08-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung ,  Chia-Hsun Tseng

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/311 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/0649 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A method of fabricating a single diffusion break includes providing a fin with two gate structures crossing the fin and a middle dummy gate structure crossing the fin, wherein the middle dummy gate structure is sandwiched by the gate structures. Later, numerous spacers are formed and each spacer respectively surrounds the gate structures and the middle dummy gate structure. Then, the middle dummy gate structure, and part of the fin directly under the middle dummy gate structure are removed to form a recess. Finally, an isolating layer in the recess is formed to close an entrance of the recess so as to form a void embedded within the recess.

Abstract translation: 制造单个扩散断裂的方法包括：提供具有与鳍片交叉的两个栅极结构的翅片和与鳍片交叉的中间伪栅极结构，其中中间伪栅极结构被栅极结构夹持。 之后，形成多个间隔物，并且每个间隔物分别围绕栅极结构和中间虚拟栅极结构。 然后，将中间的虚拟栅极结构和直接位于中间的虚拟栅极结构下面的鳍的一部分去除以形成凹部。 最后，形成凹部中的隔离层以封闭凹部的入口，以便形成嵌入凹槽内的空隙。

公开(公告)号：US09508827B2

公开(公告)日：2016-11-29

申请号：US14918583

申请日：2015-10-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jian-Cun Ke ,  Chih-Wei Yang ,  Chia-Fu Hsu

IPC: H01L21/782 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L29/49 ,  H01L21/265 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3115

CPC classification number: H01L29/66575 ,  H01L21/02532 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/28088 ,  H01L21/31155 ,  H01L29/4925 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7833

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming a lightly doped drain in the substrate; and performing a first implantation process for implanting fluorine ions at a tiled angle into the substrate and part of the gate structure.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在基板上形成栅极结构; 在衬底中形成轻掺杂漏极; 以及执行用于以平铺方式将氟离子注入所述衬底和所述栅极结构的一部分的第一注入工艺。

公开(公告)号：US20160315171A1

公开(公告)日：2016-10-27

申请号：US14727853

申请日：2015-06-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Chao-Hung Lin ,  Chih-Kai Hsu ,  Ssu-I Fu ,  Jyh-Shyang Jenq ,  Jun-Jie Wang ,  En-Chiuan Liou ,  Chih-Wei Yang ,  Chih-Sen Huang ,  Ching-Wen Hung ,  Hung-Chan Lin ,  Yu-Hsiang Lin

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653

Abstract: A method for manufacturing a semiconductor device having a metal gate includes forming a filling layer and a high-K gate dielectric layer in the first recess between a pair of spacers, wherein the high-K gate dielectric layer and the filling layer are stacked in the first recess sequentially, and an exposed top surface of the high-K gate dielectric layer and a top surface of the filling layer are lower than a top surface of each spacer; and removing a part of each spacer and widening the first recess on the top surface of the filling layer to form a second recess, wherein a width of the second recess is larger than a width of the first recess.

Abstract translation: 一种具有金属栅极的半导体器件的制造方法包括在一对间隔物之间​​的第一凹部中形成填充层和高K栅极电介质层，其中高K栅极介电层和填充层堆叠在 第一凹部，高K栅极电介质层的露出顶表面和填充层的顶表面比每个间隔物的顶表面低; 并且移除每个间隔物的一部分并加宽填充层的顶表面上的第一凹部以形成第二凹部，其中第二凹部的宽度大于第一凹部的宽度。

公开(公告)号：US20160233301A1

公开(公告)日：2016-08-11

申请号：US14663464

申请日：2015-03-20

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang

IPC: H01L29/06 ,  H01L29/10 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/324 ,  H01L29/08 ,  H01L27/088

CPC classification number: H01L21/823431 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/02667 ,  H01L21/324 ,  H01L21/3247 ,  H01L21/823412 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: The present invention provides a semiconductor structure, including a substrate, a first nanowire structure disposed on the substrate, and the first nanowire structure includes a gate region and a source/drain region The diameter of the first nanowire structure within the gate region is different from the diameter of the first nanowire structure within the source/drain region.

Abstract translation: 本发明提供一种半导体结构，包括基板，设置在基板上的第一纳米线结构，第一纳米线结构包括栅极区域和源极/漏极区域。栅极区域内的第一纳米线结构的直径不同于 源极/漏极区域内的第一纳米线结构的直径。

公开(公告)号：US09406516B2

公开(公告)日：2016-08-02

申请号：US14680078

申请日：2015-04-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jian-Cun Ke ,  Chih-Wei Yang ,  Kun-Yuan Lo ,  Chia-Fu Hsu ,  Shao-Wei Wang

IPC: H01L21/02 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7834

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a high-k dielectric layer on the interfacial layer; forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer; performing a thermal treatment; removing the first BBM layer; and forming a second BBM layer on the high-k dielectric layer.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在衬底上形成界面层; 在界面层上形成高k电介质层; 在高k电介质层上形成第一底部阻挡金属（BBM）层; 进行热处理; 去除第一个BBM层; 以及在所述高k电介质层上形成第二BBM层。

公开(公告)号：US20160093489A1

公开(公告)日：2016-03-31

申请号：US14499268

申请日：2014-09-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Feng Liu ,  Chih-Wei Yang ,  Jian-Cun Ke ,  Chia-Fu Hsu

IPC: H01L21/02 ,  H01L29/51

CPC classification number: H01L29/511 ,  H01L21/02175 ,  H01L21/02332 ,  H01L21/28185 ,  H01L21/3105 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method of forming a dielectric layer includes the following steps. First of all, a high-k dielectric layer is formed on a substrate. Next, a nitridation process is performed on the high-k dielectric layer immediately after the high-k dielectric layer is formed. Then, a post-nitridation process is performed on the high-k dielectric layer after the nitridation process is performed.

Abstract translation: 形成介电层的方法包括以下步骤。 首先，在基板上形成高k电介质层。 接下来，在形成高k电介质层之后立即在高k电介质层上进行氮化处理。 然后，在进行氮化处理之后对高k电介质层进行氮化后处理。

公开(公告)号：US20160049497A1

公开(公告)日：2016-02-18

申请号：US14918583

申请日：2015-10-21

Applicant: United Microelectronics Corp.

Inventor： Jian-Cun Ke ,  Chih-Wei Yang ,  Chia-Fu Hsu

IPC: H01L29/66 ,  H01L21/3115 ,  H01L21/28 ,  H01L21/265

CPC classification number: H01L29/66575 ,  H01L21/02532 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/28088 ,  H01L21/31155 ,  H01L29/4925 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7833

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming a lightly doped drain in the substrate; and performing a first implantation process for implanting fluorine ions at a tiled angle into the substrate and part of the gate structure.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在基板上形成栅极结构; 在衬底中形成轻掺杂漏极; 以及执行用于以平铺方式将氟离子注入所述衬底和所述栅极结构的一部分的第一注入工艺。