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    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    2.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权

    公开(公告)号：US20240413015A1

    公开(公告)日：2024-12-12

    申请号：US18220803

    申请日：2023-07-11

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Po-Kuang Hsieh ,  Chien-Ting Lin ,  Ssu-I Fu ,  Chin-Hung Chen

    IPC: H01L21/8234 ,  H01L27/088

    Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate having a low-voltage (LV) region and a medium-voltage (MV) region, forming a first metal gate on the LV region and a second metal gate on the MV region, forming a first patterned mask on the second metal gate, removing part of the first metal gate, forming a second patterned mask on the first metal gate, removing part of the second metal gate, and then forming a first hard mask on the first metal gate and a second hard mask on the second metal gate.

    STRUCTURE OF SEMICONDUCTOR DEVICE
    7.
    发明申请
    STRUCTURE OF SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220093741A1

    公开(公告)日：2022-03-24

    申请号：US17511579

    申请日：2021-10-27

    Applicant: United Microelectronics Corp.

    Inventor： Chia-Jung Hsu ,  Chin-Hung Chen ,  Chun-Ya Chiu ,  Chih-Kai Hsu ,  Ssu-I Fu ,  Tsai-Yu Wen ,  Shi You Liu ,  Yu-Hsiang Lin

    IPC: H01L29/10 ,  H01L21/265 ,  H01L29/06 ,  H01L29/167

    Abstract: A structure of semiconductor device is provided, including a substrate. First and second trench isolations are disposed in the substrate. A height of a portion of the substrate is between a top and a bottom of the first and second trench isolations. A gate insulation layer is disposed on the portion of the substrate between the first and second trench isolations. A first germanium (Ge) doped layer region is disposed in the portion of the substrate just under the gate insulation layer. A second Ge doped layer region is in the portion of the substrate, overlapping with the first Ge doped layer region to form a Ge gradient from high to low along a depth direction under the gate insulation layer. A fluorine (F) doped layer region is in the portion of the substrate, lower than and overlapping with the first germanium doped layer region.

    Semiconductor device and manufacturing method thereof
    8.
    发明授权
    Semiconductor device and manufacturing method thereof 有权

    公开(公告)号：US11152515B2

    公开(公告)日：2021-10-19

    申请号：US16572556

    申请日：2019-09-16

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chin-Hung Chen ,  Ssu-I Fu ,  Chih-Kai Hsu ,  Chun-Ya Chiu ,  Chia-Jung Hsu ,  Yu-Hsiang Lin

    IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/306 ,  H01L21/02

    Abstract: A manufacturing method of a semiconductor device includes the following steps. An opening is formed penetrating a dielectric layer on a semiconductor substrate. A stacked structure is formed on the dielectric layer. The stacked structure includes a first semiconductor layer partly formed in the opening and partly formed on the dielectric layer, a sacrificial layer formed on the first semiconductor layer, and a second semiconductor layer formed on the sacrificial layer. A patterning process is performed for forming a fin-shaped structure including the first semiconductor layer, the sacrificial layer, and the second semiconductor layer. An etching process is performed to remove the sacrificial layer in the fin-shaped structure. The first semiconductor layer in the fin-shaped structure is etched to become a first semiconductor wire by the etching process. The second semiconductor layer in the fin-shaped structure is etched to become a second semiconductor wire by the etching process.

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