公开(公告)号：US20250151366A1

公开(公告)日：2025-05-08

申请号：US18531679

申请日：2023-12-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zi-Ting Huang ,  Ching-Ling Lin ,  Wen-An Liang

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a core region and an input/output (I/O) region and then forming a first metal gate on the core region and a second metal gate on the I/O region. Preferably, the first metal gate includes a first gate dielectric layer, the second metal gate includes a second gate dielectric layer, the first gate dielectric layer and the second gate dielectric layer having different shapes such that the first gate dielectric layer includes an I-shape and the second gate dielectric layer includes a U-shape.

公开(公告)号：US20250132168A1

公开(公告)日：2025-04-24

申请号：US18513669

申请日：2023-11-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Ching Chen ,  Ching-Ling Lin ,  Wen-An Liang

IPC: H01L21/3213 ,  H01L21/3205 ,  H01L21/321 ,  H01L29/66

Abstract: A planarization method includes the following steps. A silicon layer is deposited on a substrate, and a top surface of the silicon layer includes a lower portion and a bump portion protruding upwards from the lower portion. An ion bombardment etching process is performed to the silicon layer for reducing a surface step height of the silicon layer. The top surface of the silicon layer is etched by the ion bombardment etching process to become a post-etching top surface, and a distance between a topmost portion of the post-etching top surface and a bottommost portion of the post-etching top surface in a vertical direction is less than a distance between a topmost portion of the bump portion and the lower portion in the vertical direction before the ion bombardment etching process. Subsequently, a chemical mechanical polishing process is performed to the post-etching top surface of the silicon layer.

公开(公告)号：US20190019731A1

公开(公告)日：2019-01-17

申请号：US15647031

申请日：2017-07-11

Applicant: United Microelectronics Corp.

Inventor： Ching-Ling Lin ,  Wen-An Liang ,  Chen-Ming Huang

IPC: H01L21/8234 ,  H01L21/033

Abstract: A method for fabricating a semiconductor structure includes forming a plurality of mandrels over a substrate, wherein the substrate comprises a semiconductor substrate as a base. Then, a first dielectric layer is formed to cover on a predetermined mandrel of the mandrels. A second dielectric layer is formed over the substrate to cover the mandrels. The mandrels are removed, wherein a remaining portion of the first dielectric layer and the second dielectric layer at a sidewall of the mandrels remains on the substrate. An anisotropic etching process is performed over the substrate until a top portion of the semiconductor substrate is etched to form a plurality of fins corresponding to the remaining portion of the first dielectric layer and the second dielectric layer.

公开(公告)号：US09748144B1

公开(公告)日：2017-08-29

申请号：US15138228

申请日：2016-04-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Yi-Wen Chen ,  Chen-Ming Huang ,  Ren-Peng Huang ,  Ching-Fu Lin

IPC: H01L21/00 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/3213 ,  H01L29/423 ,  H01L21/321 ,  H01L21/033 ,  H01L29/51 ,  H01L21/28 ,  H01L27/11

CPC classification number: H01L21/823456 ,  H01L21/0332 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/31055 ,  H01L21/32115 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/1104 ,  H01L27/1116 ,  H01L28/00 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: First and second semiconductor structures, a CESL, and an ILD layer are formed on a substrate. The first semiconductor structure includes first dummy gate, first nitride mask, and first oxide mask. The second semiconductor structure includes second dummy gate, second nitride mask, and second oxide mask. A first planarization is performed to remove a portion of the ILD layer, exposing CESL. A portion of the CESL, a portion of the ILD layer, the first and the second oxide masks are removed. A hard mask layer is formed on the first and the second nitride masks, and in a recess of the ILD layer. A second planarization is performed to remove a portion of the hard mask layer, the first and the second nitride masks, exposing first and second dummy gates. A remaining portion of the hard mask layer covers the ILD layer.

公开(公告)号：US20140302677A1

公开(公告)日：2014-10-09

申请号：US13859720

申请日：2013-04-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Chien-Ting Lin

IPC: H01L21/311 ,  H01L21/3105

CPC classification number: H01L21/3086 ,  H01L21/823468 ,  H01L21/823864 ,  H01L29/66795

Abstract: A method for manufacturing semiconductor structures includes providing a substrate having a plurality of mandrel patterns and a plurality of dummy patterns, simultaneously forming a plurality of first spacers on sidewalls of the mandrel patterns and a plurality of second spacers on sidewalls of the dummy patterns, and removing the second spacers and the mandrel patterns to form a plurality of spacer patterns on the substrate.

Abstract translation: 一种用于制造半导体结构的方法，包括提供具有多个心轴图案和多个虚拟图案的基板，同时在心轴图案的侧壁上形成多个第一间隔件，在虚设图案的侧壁上形成多个第二间隔件，以及 移除第二间隔件和心轴图案以在基底上形成多个间隔图案。

公开(公告)号：US20140295650A1

公开(公告)日：2014-10-02

申请号：US13851113

申请日：2013-03-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Jung Li ,  Chia-Jui Liang ,  Po-Chao Tsao ,  Ching-Ling Lin ,  En-Chiuan Liou

IPC: H01L21/308 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/308 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76229

Abstract: A method of fabricating a patterned structure of a semiconductor device is provided. First, a substrate having a first region and a second region is provided. A target layer, a hard mask layer and a first patterned mask layer are then sequentially formed on the substrate. A first etching process is performed by using the first patterned mask layer as an etch mask so that a patterned hard mask layer is therefore formed. Spacers are respectively formed on each sidewall of the patterned hard mask layer. Then, a second patterned mask layer is formed on the substrate. A second etching process is performed to etch the patterned hard mask layer in the second region. After the exposure of the spacers, the patterned hard mask layer is used as an etch mask and an exposed target layer is removed until the exposure of the corresponding substrate.

Abstract translation: 提供一种制造半导体器件的图案化结构的方法。 首先，提供具有第一区域和第二区域的基板。 然后在基板上顺序地形成目标层，硬掩模层和第一图案化掩模层。 通过使用第一图案化掩模层作为蚀刻掩模来执行第一蚀刻工艺，从而形成图案化的硬掩模层。 间隔物分别形成在图案化的硬掩模层的每个侧壁上。 然后，在基板上形成第二图案化掩模层。 执行第二蚀刻工艺以蚀刻第二区域中的图案化硬掩模层。 在间隔物曝光之后，将图案化的硬掩模层用作蚀刻掩模，并且去除曝光的目标层，直到相应的基板的曝光。

公开(公告)号：US20250098252A1

公开(公告)日：2025-03-20

申请号：US18379667

申请日：2023-10-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ke-Ting Chen ,  Ching-Ling Lin ,  Wen-An Liang ,  Chia-Fu Hsu

IPC: H01L29/40 ,  H01L21/311 ,  H01L29/417 ,  H01L29/423

Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a contact etch stop layer (CESL) adjacent to the metal gate, and an interlayer dielectric (ILD) layer around the gate structure, performing a first etching process to remove the ILD layer, performing a second etching process to remove the CESL for forming a first contact hole, and then forming a first contact plug in the first contact hole. Preferably, a width of the first contact plug adjacent to the CESL is less than a width of the first contact plug under the CESL.

公开(公告)号：US20240371699A1

公开(公告)日：2024-11-07

申请号：US18208896

申请日：2023-06-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Wen-An Liang ,  Chia-Fu Hsu ,  Huang-Ren Wei

IPC: H01L21/8234 ,  H01L21/768 ,  H01L23/528 ,  H01L27/088 ,  H01L29/66

Abstract: The invention provides a semiconductor structure, the semiconductor structure comprises a substrate, a dielectric layer located on the substrate, a plurality of gate structures located in the dielectric layer on the substrate, a plurality of first metal layers located on a part of the gate structures, and the first metal layers are respectively electrically connected with the corresponding gate structures, at least one second metal layer, the second metal layer is bridged over at least two of the gate structures, wherein the depth of the first metal layer is greater than that of the second metal layer.

公开(公告)号：US20200328126A1

公开(公告)日：2020-10-15

申请号：US16914483

申请日：2020-06-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Jung Chuang ,  Ching-Ling Lin ,  Po-Jen Chuang ,  Yu-Ren Wang ,  Wen-An Liang ,  Chia-Ming Kuo ,  Guan-Wei Huang ,  Yuan-Yu Chung ,  I-Ming Tseng

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/762

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate having a n-type work function metal layer or a p-type work function metal layer.

公开(公告)号：US10679903B2

公开(公告)日：2020-06-09

申请号：US15859775

申请日：2018-01-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Wen-An Liang ,  Chen-Ming Huang

IPC: H01L21/8234 ,  H01L21/764 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a first gate structure and a second gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; transforming the first gate structure and the second gate structure into a first metal gate and a second metal gate; forming a hard mask on the first metal gate and the second metal gate; removing part of the hard mask, the second metal gate, and part of the fin-shaped structure to form a trench; and forming a dielectric layer into the trench to form a single diffusion break (SDB) structure.