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公开(公告)号：US20170194314A1
公开(公告)日：2017-07-06
申请号：US15007163
申请日：2016-01-26
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ching-Wei Lee , Li-Cih Wang , Tien-Hao Tang
CPC classification number: H01L27/0262 , H01L29/0619 , H01L29/0649 , H01L29/7436 , H01L29/861
Abstract: An ESD protection semiconductor device includes a substrate, a buried layer buried in the substrate, a first well formed in the substrate, a first doped region formed in the first well, a second doped region formed in the first well and adjacent to the first doped region, a second well formed in the first well, and a third doped region formed in the second well. The buried layer, the first well, the first doped region, and the third doped region include a first conductivity type while the second doped region and the second well include a second conductivity type complementary to the first conductivity type. The second well is spaced apart from the first doped region and the second doped region by the first well.
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公开(公告)号：US09859271B2
公开(公告)日：2018-01-02
申请号：US15007163
申请日：2016-01-26
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ching-Wei Lee , Li-Cih Wang , Tien-Hao Tang
CPC classification number: H01L27/0262 , H01L29/0619 , H01L29/0649 , H01L29/7436 , H01L29/861
Abstract: An ESD protection semiconductor device includes a substrate, a buried layer buried in the substrate, a first well formed in the substrate, a first doped region formed in the first well, a second doped region formed in the first well and adjacent to the first doped region, a second well formed in the first well, and a third doped region formed in the second well. The buried layer, the first well, the first doped region, and the third doped region include a first conductivity type while the second doped region and the second well include a second conductivity type complementary to the first conductivity type. The second well is spaced apart from the first doped region and the second doped region by the first well.
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