公开(公告)号：US20230352565A1

公开(公告)日：2023-11-02

申请号：US18218599

申请日：2023-07-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Chang Hsu ,  Chun-Chia Chen ,  Yao-Jhan Wang ,  Chun-Jen Huang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L21/768 ,  H01L21/28 ,  H01L21/8238

CPC classification number: H01L29/6656 ,  H01L29/66795 ,  H01L29/66545 ,  H01L29/6653 ,  H01L29/7851 ,  H01L29/4983 ,  H01L29/4966 ,  H01L21/76834 ,  H01L29/4958 ,  H01L21/28247 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/823821 ,  H01L29/7848 ,  H01L29/0847

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; forming a first contact etch stop layer (CESL) around the spacer; forming a mask layer on the first CESL; removing part of the mask layer; removing part of the first CESL; forming a second CESL on the mask layer and the gate structure; and removing part of the second CESL.

公开(公告)号：US20230207669A1

公开(公告)日：2023-06-29

申请号：US18118154

申请日：2023-03-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Fu Chang ,  Kuan-Hung Chen ,  Guang-Yu Lo ,  Chun-Chia Chen ,  Chun-Tsen Lu

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L29/66795 ,  H01L29/785 ,  H01L29/7834 ,  H01L29/511 ,  H01L21/022 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/28202

Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.

公开(公告)号：US11631753B2

公开(公告)日：2023-04-18

申请号：US16282323

申请日：2019-02-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Fu Chang ,  Kuan-Hung Chen ,  Guang-Yu Lo ,  Chun-Chia Chen ,  Chun-Tsen Lu

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28

Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.

公开(公告)号：US20200235227A1

公开(公告)日：2020-07-23

申请号：US16282323

申请日：2019-02-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Fu Chang ,  Kuan-Hung Chen ,  Guang-Yu Lo ,  Chun-Chia Chen ,  Chun-Tsen Lu

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L21/02 ,  H01L29/51

Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.

公开(公告)号：US20200235224A1

公开(公告)日：2020-07-23

申请号：US16836872

申请日：2020-03-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Chang Hsu ,  Chun-Chia Chen ,  Yao-Jhan Wang

IPC: H01L29/66 ,  H01L21/3105 ,  H01L21/3115 ,  H01L21/02 ,  H01L21/768

Abstract: A semiconductor device includes a gate structure on a substrate, an offset spacer adjacent to the gate structure, a main spacer around the offset spacer, a source/drain region adjacent to two sides of the main spacer, a contact etch stop layer (CESL) adjacent to the main spacer, and an interlayer dielectric (ILD) layer around the CESL. Preferably, a dielectric constant of the offset spacer is higher than a dielectric constant of the main spacer.

公开(公告)号：US10211314B1

公开(公告)日：2019-02-19

申请号：US15790043

申请日：2017-10-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Chang Hsu ,  Chun-Chia Chen ,  Yao-Jhan Wang

IPC: H01L21/28 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/3115

Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a contact etch stop layer (CESL) on the gate structure, forming an interlayer dielectric (ILD) layer around the gate structure, performing a curing process so that an oxygen concentration of the CESL is different from the oxygen concentration of the ILD layer, and then performing a replacement metal gate process (RMG) process to transform the gate structure into a metal gate.

公开(公告)号：US20230207668A1

公开(公告)日：2023-06-29

申请号：US18118115

申请日：2023-03-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Fu Chang ,  Kuan-Hung Chen ,  Guang-Yu Lo ,  Chun-Chia Chen ,  Chun-Tsen Lu

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L29/66795 ,  H01L29/785 ,  H01L29/7834 ,  H01L29/511 ,  H01L21/022 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/28202

Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.

公开(公告)号：US20190058050A1

公开(公告)日：2019-02-21

申请号：US15710820

申请日：2017-09-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Chang Hsu ,  Chun-Chia Chen ,  Yao-Jhan Wang ,  Chun-Jen Huang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; forming a first contact etch stop layer (CESL) around the spacer; forming a mask layer on the first CESL; removing part of the mask layer; removing part of the first CESL; forming a second CESL on the mask layer and the gate structure; and removing part of the second CESL.

公开(公告)号：US10037915B1

公开(公告)日：2018-07-31

申请号：US15700171

申请日：2017-09-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Chang Hsu ,  Chun-Chia Chen ,  Yao-Jhan Wang

IPC: H01L21/8234 ,  H01L29/78

CPC classification number: H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A fabricating method of a semiconductor structure includes providing a substrate divided into a dense region and an isolated region, wherein a first gate structure is disposed within the dense region, and a second gate structure is disposed within the isolated region. Then, a first material layer is formed to cover the first gate structure, the second gate structure and the substrate. Later, a second material layer is formed to cover the first material layer. After that, the second material layer within the dense region is entirely removed. Subsequently, a third material layer is formed to cover the isolated region and the dense region. Next, the substrate is etched to forma first recess at two sides of the first gate structure, and a second recess at two sides of the second gate structure. Finally, an epitaxial layer is formed to fill the first recess and the second recess.

公开(公告)号：US09685520B1

公开(公告)日：2017-06-20

申请号：US15355032

申请日：2016-11-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shuo-Lin Hsu ,  Hsin-Ta Hsieh ,  Chun-Chia Chen ,  Chen-Chien Li ,  Hung-Chang Chang ,  Ta-Kang Lo ,  Tsai-Fu Chen ,  Shang-Jr Chen

IPC: H01L21/00 ,  H01L29/423 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L29/4966 ,  H01L21/82345 ,  H01L21/823842 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66666

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first gate dielectric layer is formed in a first gate trench and a second gate dielectric layer is formed in a second gate trench. A first bottom barrier layer is formed on the first gate dielectric layer and the second gate dielectric layer. A first conductivity type work function layer is formed on the first bottom barrier layer. A first treatment to the first gate dielectric layer and/or a second treatment to the first bottom barrier layer on the first gate dielectric layer are performed before the step of forming the first conductivity type work function layer. The first treatment and the second treatment are used to modify threshold voltages of specific transistors, and thicknesses of work function layers formed subsequently may be modified for increasing the related process window accordingly.