公开(公告)号：US20250113494A1

公开(公告)日：2025-04-03

申请号：US18979625

申请日：2024-12-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Yi-An Shih ,  Bin-Siang Tsai ,  Fu-Yu Tsai

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/80

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a top electrode on the MTJ, forming an inter-metal dielectric (IMD) layer around the top electrode and the MTJ, forming a landing layer on the IMD layer and the MTJ, and then patterning the landing layer to form a landing pad. Preferably, the landing pad is disposed on the top electrode and the IMD layer adjacent to one side of the top electrode.

公开(公告)号：US20250054883A1

公开(公告)日：2025-02-13

申请号：US18244320

申请日：2023-09-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Fu-Yu Tsai ,  Chung-Yi Chiu

IPC: H01L23/64 ,  H01L23/498

Abstract: An interposer includes a substrate having an inductor forming region thereon, a plurality of trenches within the inductor forming region in the substrate, a buffer layer lining interior surfaces of the plurality of trenches and forming air gaps within the plurality of trenches, and an inductor coil pattern embedded in the buffer layer within the inductor forming region.

公开(公告)号：US20250008842A1

公开(公告)日：2025-01-02

申请号：US18885729

申请日：2024-09-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tai-Cheng Hou ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Da-Jun Lin ,  Chau-Chung Hou ,  Wei-Xin Gao

IPC: H10N50/01 ,  H10B61/00 ,  H10N50/80

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a MRAM region and a logic region; forming a magnetic tunneling junction (MTJ) on the MRAM region; forming a top electrode on the MTJ; and then performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ.

公开(公告)号：US20240213304A1

公开(公告)日：2024-06-27

申请号：US18107521

申请日：2023-02-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Fu-Yu Tsai ,  Chung-Yi Chiu

IPC: H01L27/06 ,  H01L21/285 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L28/60 ,  H01L21/28556 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L27/0629 ,  H01L27/0647

Abstract: An MIM capacitor structure includes numerous inter-metal dielectrics. A trench is embedded within the inter-metal dielectrics. A capacitor is disposed within the trench. The capacitor includes a first electrode layer, a capacitor dielectric layer and a second electrode layer. The first electrode layer, the capacitor dielectric layer and the second electrode layer fill in and surround the trench. The capacitor dielectric layer is between the first electrode layer and the second electrode layer. A silicon oxide liner surrounds a sidewall of the trench and contacts the first electrode layer.

公开(公告)号：US11871677B2

公开(公告)日：2024-01-09

申请号：US17180876

申请日：2021-02-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tai-Cheng Hou ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Da-Jun Lin ,  Chau-Chung Hou ,  Wei-Xin Gao

IPC: H10N50/01 ,  H10B61/00 ,  H10N50/80

CPC classification number: H10N50/01 ,  H10B61/00 ,  H10N50/80

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a MRAM region and a logic region; forming a magnetic tunneling junction (MTJ) on the MRAM region; forming a top electrode on the MTJ; and then performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ.

公开(公告)号：US20230369436A1

公开(公告)日：2023-11-16

申请号：US17837054

申请日：2022-06-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chung-Yi Chiu

IPC: H01L29/45 ,  H01L21/285 ,  H01L29/66 ,  H01L29/778 ,  H01L29/20

CPC classification number: H01L29/452 ,  H01L21/28575 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/2003

Abstract: A method for forming ohmic contacts on a compound semiconductor device is disclosed. A channel layer is formed on a substrate. A barrier layer is formed on the channel layer. A passivation layer is formed on the barrier layer. A contact area is formed by etching through the passivation layer and the barrier layer. The channel layer is partially exposed at a bottom of the contact area. A sacrificial metallic layer is conformally deposited on the contact area. The sacrificial metallic layer is subjected to an annealing process, thereby forming a heavily doped region in the channel layer directly under the sacrificial metallic layer. The sacrificial metallic layer is removed to expose the heavily doped region. A metal silicide layer is formed on the heavily doped region.

公开(公告)号：US20230369435A1

公开(公告)日：2023-11-16

申请号：US17835956

申请日：2022-06-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chung-Yi Chiu

IPC: H01L29/45 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/40 ,  H01L21/285 ,  H01L29/66

CPC classification number: H01L29/452 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7786 ,  H01L29/401 ,  H01L21/28575 ,  H01L29/66462

Abstract: A compound semiconductor device includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, a passivation layer on the barrier layer, and a contact area recessed into the passivation layer and the barrier layer. The channel layer is partially exposed at a bottom of the contact area. A bi-layer silicide film is disposed on the contact area. A copper contact is disposed on the bi-layer silicide film.

公开(公告)号：US20230329004A1

公开(公告)日：2023-10-12

申请号：US18209482

申请日：2023-06-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Yi-An Shih ,  Bin-Siang Tsai ,  Fu-Yu Tsai

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10B61/00 ,  H10N50/01 ,  H10N50/80

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a top electrode on the MTJ, forming an inter-metal dielectric (IMD) layer around the top electrode and the MTJ, forming a landing layer on the IMD layer and the MTJ, and then patterning the landing layer to form a landing pad. Preferably, the landing pad is disposed on the top electrode and the IMD layer adjacent to one side of the top electrode.

公开(公告)号：US11707003B2

公开(公告)日：2023-07-18

申请号：US17140981

申请日：2021-01-04

Applicant: United Microelectronics Corp.

Inventor： Chich-Neng Chang ,  Da-Jun Lin ,  Shih-Wei Su ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC: H10N70/20 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/24 ,  H10B63/30 ,  H10N70/063 ,  H10N70/826 ,  H10N70/841

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a device substrate, a resistance variable layer and a top electrode. The bottom electrode is disposed on the device substrate. The resistance variable layer is disposed on the bottom electrode. The top electrode is disposed on the resistance variable layer. The bottom electrode is formed with a tensile stress, while the top electrode is formed with a compressive stress.

公开(公告)号：US11676920B2

公开(公告)日：2023-06-13

申请号：US17159080

申请日：2021-01-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Fu-Yu Tsai

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/45 ,  H01L2224/05124 ,  H01L2224/45147 ,  H01L2224/45464

Abstract: A method for fabricating a semiconductor device includes the steps of first forming an aluminum (Al) pad on a substrate, forming a passivation layer on the substrate and an opening exposing the Al pad, forming a cobalt (Co) layer in the opening and on the Al pad, bonding a wire onto the Co layer, and then performing a thermal treatment process to form a Co—Pd alloy on the Al pad.