公开(公告)号：US12266723B2

公开(公告)日：2025-04-01

申请号：US18596643

申请日：2024-03-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Hsiao Chen ,  Kai-Lin Lee

IPC: H01L29/778 ,  H01L29/06 ,  H01L29/20 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, a buffer layer disposed on the substrate, a channel layer disposed on the buffer layer, a barrier layer disposed on the buffer layer, and a passivation layer disposed on the barrier layer. The semiconductor device further includes a device isolation region that extends through the passivation layer, the barrier layer, and at least a portion of the channel layer, and encloses a first device region of the semiconductor device. A damage concentration of the device isolation region varies along a depth direction, and is highest near a junction between the barrier layer and the channel layer.

公开(公告)号：US20240421219A1

公开(公告)日：2024-12-19

申请号：US18815864

申请日：2024-08-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Lin Lee ,  Zhi-Cheng Lee ,  Wei-Jen Chen

IPC: H01L29/778 ,  H01L21/02 ,  H01L21/308 ,  H01L29/20 ,  H01L29/66

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess.

公开(公告)号：US12107121B2

公开(公告)日：2024-10-01

申请号：US17515563

申请日：2021-11-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Cheng Lee ,  Chuang-Han Hsieh ,  Kai-Lin Lee

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L21/823418 ,  H01L21/823481 ,  H01L29/0847 ,  H01L29/515 ,  H01L29/7851

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a gate dielectric layer on a substrate, forming a gate material layer on the gate dielectric layer, patterning the gate material layer and the gate dielectric layer to form a gate structure, removing a portion of the gate dielectric layer, forming a spacer adjacent to the gate structure and at the same time forming an air gap between the gate dielectric layer and the spacer, and then forming a source/drain region adjacent to two sides of the spacer.

公开(公告)号：US20220285522A1

公开(公告)日：2022-09-08

申请号：US17824917

申请日：2022-05-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Cheng Lee ,  Wei-Jen Chen ,  Kai-Lin Lee ,  Tai-Ju Chen

IPC: H01L29/66 ,  H01L29/06

Abstract: A semiconductor substrate is provided. A trench isolation region is formed in the semiconductor substrate. A resist pattern having an opening exposing the trench isolation region and partially exposing the semiconductor substrate is disposed adjacent to the trench isolation region. A first ion implantation process is performed to implant first dopants into the semiconductor substrate through the opening, thereby forming a well region in the semiconductor substrate. The trench isolation region is within the well region. A second ion implantation process is performed to implant second dopants into the semiconductor substrate through the opening, thereby forming an extended doped region contiguous with the well region. The resist pattern is then removed. After removing the resist pattern, a gate dielectric layer is formed on the semiconductor substrate. A gate is then formed on the gate dielectric layer. The gate overlaps with the extended doped region.

公开(公告)号：US20220271161A1

公开(公告)日：2022-08-25

申请号：US17216642

申请日：2021-03-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ling-Chun Chou ,  Te-Chi Yen ,  Yu-Hung Chang ,  Kun-Hsien Lee ,  Kai-Lin Lee

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08

Abstract: A high voltage semiconductor device includes a semiconductor substrate, first and second deep well regions, and first and second well regions disposed in the semiconductor substrate. The second deep well region is located above the first deep well region. The first well region is located above the first deep well region. The second well region is located above the second deep well region. A conductivity type of the second deep well region is complementary to that of the first deep well region. A conductivity type of the second well region is complementary to that of the first well region and the second deep well region. A length of the second deep well region is greater than or equal to that of the second well region and less than that of the first deep well region. The first well region is connected with the first deep well region.

公开(公告)号：US20210376121A1

公开(公告)日：2021-12-02

申请号：US17402608

申请日：2021-08-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Cheng Lee ,  Wei-Jen Chen ,  Kai-Lin Lee

IPC: H01L29/66

Abstract: A method of fabricating a metal gate transistor includes providing a substrate. An interlayer dielectric layer covers the substrate. A dummy gate is embedded in the interlayer dielectric layer. A high-k dielectric layer is disposed between the dummy gate and the substrate. Later, the dummy gate is removed to form a trench, and the high-k dielectric layer is exposed through the trench. After the dummy gate is removed, an ion implantation process is performed to implant fluoride ions into the high-k dielectric layer. Finally, after the ion implantation process, a metal gate is formed to fill in the trench.

公开(公告)号：US20200295176A1

公开(公告)日：2020-09-17

申请号：US16361231

申请日：2019-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Cheng Lee ,  Wei-Jen Chen ,  Kai-Lin Lee

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/165 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor structure includes at least one stacked fin structure, a gate and a source/drain. At least one stacked fin structure is located on a substrate, wherein the stacked fin structure includes a first fin layer and a second fin layer, and a fin dielectric layer is sandwiched by the first fin layer and the second fin layer. The gate is disposed over the stacked fin structure. The source/drain is disposed directly on the substrate and directly on sidewalls of the whole stacked fin structure. The present invention provides a semiconductor process formed said semiconductor structure.

公开(公告)号：US10229995B2

公开(公告)日：2019-03-12

申请号：US15668719

申请日：2017-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Lin Lee ,  Zhi-Cheng Lee ,  Wei-Jen Chen ,  Ting-Hsuan Kang ,  Ren-Yu He ,  Hung-Wen Huang ,  Chi-Hsiao Chen ,  Hao-Hsiang Yang ,  An-Shih Shih ,  Chuang-Han Hsieh

IPC: H01L29/76 ,  H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/762

Abstract: A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.

公开(公告)号：US12132095B2

公开(公告)日：2024-10-29

申请号：US18129099

申请日：2023-03-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Cheng Lee ,  Wei-Jen Chen ,  Kai-Lin Lee

IPC: H01L29/66

CPC classification number: H01L29/66545

Abstract: A method of fabricating a metal gate transistor includes providing a substrate. Then, a high-k dielectric layer is formed to cover the substrate. Later, an ion implantation process is performed to implant fluoride ions into the high-k dielectric layer. After the ion implantation process, a polysilicon gate is formed on the high-k dielectric layer. Next, an interlayer dielectric layer is formed to cover the substrate and the polysilicon gate. Finally, the polysilicon gate is replaced by a metal gate.

公开(公告)号：US11239327B2

公开(公告)日：2022-02-01

申请号：US16513699

申请日：2019-07-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Lin Lee ,  Zhi-Cheng Lee ,  Wei-Jen Chen

IPC: H01L29/40 ,  H01L21/02 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778

Abstract: A high electron mobility transistor (HEMT) includes a gallium nitride layer. An aluminum gallium nitride layer is disposed on the gallium nitride layer, wherein the aluminum gallium nitride layer comprises a tensile stress. A source electrode and a drain electrode are disposed on the aluminum gallium nitride layer. A gate electrode is disposed on the aluminum gallium nitride layer between the source electrode and the drain electrode. At least one silicon oxide layer is embedded in the aluminum gallium nitride layer, wherein the silicon oxide layer is formed by a flowable chemical vapor deposition, and the silicon oxide layer increases the tensile stress in the aluminum gallium nitride layer.