公开(公告)号：US09213800B1

公开(公告)日：2015-12-15

申请号：US14474180

申请日：2014-08-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Chih Chang ,  Kuo-Hsun Huang ,  Chao-Yao Chiang

IPC: G06F17/50

CPC classification number: G03F1/36 ,  G03F1/68

Abstract: The optical proximity correction verification method includes loading a layout data to be verified to a processor, loading a reference layout data to the processor. The processor performs a first stage Boolean operation on the layout data to be verified to generate first verified data. The processor performs a layout versus layout verification on the first verified data to generate second verified data by using the reference layout data. If the layout versus layout verification is successfully performed, the processor performs a second stage Boolean operation on the second verified data to generate third verified data. By using the reference layout data, the processor performs a Boolean check on the third verified data to generate fourth verified data.

Abstract translation: 光学邻近校正验证方法包括将要验证的布局数据加载到处理器，将参考布局数据加载到处理器。 处理器对待验证的布局数据执行第一阶段布尔运算，以生成第一验证数据。 处理器对第一验证数据执行布局与布局验证，以通过使用参考布局数据生成第二验证数据。 如果布局与布局验证成功执行，则处理器对第二验证数据执行第二阶段布尔运算以产生第三验证数据。 通过使用参考布局数据，处理器对第三验证数据执行布尔检查，以生成第四验证数据。

公开(公告)号：US09147035B1

公开(公告)日：2015-09-29

申请号：US14533471

申请日：2014-11-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsun Huang ,  Chao-Yao Chiang ,  Chien-Hung Chen

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F1/70

Abstract: A verifying method of an optical proximity correction is provided. The verifying method includes the following steps. A first netlist file is extracted from an integrated pre-OPC layout. A first post-OPC layout and a second post-OPC layout are merged to be an integrated post-OPC layout. A second netlist file is extracted from the integrated post-OPC layout. The first netlist file and the second netlist are compared.

Abstract translation: 提供了光学邻近校正的验证方法。 验证方法包括以下步骤。 从集成的前OPC布局中提取第一个网表文件。 第一个后OPC布局和第二个后OPC布局被合并为一个集成的OPC后布局。 从集成的后OPC布局中提取第二个网表文件。 比较第一个网表文件和第二个网表。

公开(公告)号：US20160063173A1

公开(公告)日：2016-03-03

申请号：US14935464

申请日：2015-11-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Chih Chang ,  Kuo-Hsun Huang ,  Chao-Yao Chiang

IPC: G06F17/50 ,  G03F1/36

CPC classification number: G03F1/36 ,  G03F1/68

Abstract: The optical proximity correction verification method includes loading a layout data to be verified to a processor, loading a reference layout data to the processor. The processor performs a first stage Boolean operation on the layout data to be verified to generate a first verified data. The processor performs a layout versus layout verification on the first verified data by using a user-defined verification tool of optical proximity correction data in a database to generate second verified data according to the reference layout data. The processor performs a second stage Boolean operation on the second verified data to generate a third verified data if the layout versus layout verification is successfully performed. The processor performs a Boolean check on the third verified data to generate fourth verified data using the reference layout data.

Abstract translation: 光学邻近校正验证方法包括将要验证的布局数据加载到处理器，将参考布局数据加载到处理器。 处理器对待验证的布局数据执行第一阶段布尔运算以生成第一验证数据。 处理器通过使用数据库中的光学邻近校正数据的用户定义的验证工具对第一验证数据执行布局与布局验证，以根据参考布局数据生成第二验证数据。 如果成功执行布局对布局验证，则处理器对第二验证数据执行第二阶段布尔运算以产生第三验证数据。 处理器对第三个验证数据执行布尔检查，以使用参考布局数据生成第四个验证数据。

公开(公告)号：US09245079B1

公开(公告)日：2016-01-26

申请号：US14324231

申请日：2014-07-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsun Huang ,  Hsi-Chang Chang ,  Chao-Yao Chiang ,  Chien-Hung Chen

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/504 ,  G06F17/5081

Abstract: A computer implemented method for performing extraction is provided in the present invention. First, a layout of a semiconductor circuit having a resistor is imported by using a computer wherein a device region is defined in the layout and the resistor is located within the device region. Next, the device region of the layout are extracted, and a compensation value of Rs (Rc) is obtained according to the extracting step. An adjustment process is performed according to Rc to obtained a refined R value.

Abstract translation: 本发明提供了一种用于执行提取的计算机实现方法。 首先，通过使用其中在布局中限定器件区域并且电阻器位于器件区域内的计算机来导入具有电阻器的半导体电路的布局。 接下来，提取布局的设备区域，并且根据提取步骤获得Rs（Rc）的补偿值。 根据Rc执行调整处理以获得精确的R值。

公开(公告)号：US20150356231A1

公开(公告)日：2015-12-10

申请号：US14337187

申请日：2014-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chao-Yao Chiang ,  Kuo-Hsun Huang ,  Chien-Hung Chen

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5068

Abstract: A planar design to non-planar design conversion method includes following steps. At least a diffusion region pattern including a first side and a second side perpendicular to each other is received. A look-up table is queried to obtain a first positive integer according to the first side of the diffusion region pattern and a second positive integer according to the second side of the diffusion region pattern. Then, a plurality of fin patterns is formed. An amount of the fin patterns is equal to the second positive integer. The fin patterns respectively include a first fin length, and the first fin length is a product of the first positive integer and a predetermined value. The forming is performed by at least a computer-aided design (CAD) tool.

Abstract translation: 非平面设计转换方法的平面设计包括以下步骤。 至少包括彼此垂直的第一侧和第二侧的扩散区图案。 查询表根据扩散区域图案的第一侧获得第一正整数，并根据扩散区图案的第二侧获得第二正整数。 然后，形成多个翅片图案。 鳍图案的数量等于第二正整数。 翅片图案分别包括第一翅片长度，并且第一翅片长度是第一正整数和预定值的乘积。 至少由计算机辅助设计（CAD）工具进行成型。

公开(公告)号：US09330229B2

公开(公告)日：2016-05-03

申请号：US14935464

申请日：2015-11-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Chih Chang ,  Kuo-Hsun Huang ,  Chao-Yao Chiang

IPC: G06F17/50 ,  G03F1/36

CPC classification number: G03F1/36 ,  G03F1/68

Abstract: The optical proximity correction verification method includes loading a layout data to be verified to a processor, loading a reference layout data to the processor. The processor performs a first stage Boolean operation on the layout data to be verified to generate a first verified data. The processor performs a layout versus layout verification on the first verified data by using a user-defined verification tool of optical proximity correction data in a database to generate second verified data according to the reference layout data. The processor performs a second stage Boolean operation on the second verified data to generate a third verified data if the layout versus layout verification is successfully performed. The processor performs a Boolean check on the third verified data to generate fourth verified data using the reference layout data.

Abstract translation: 光学邻近校正验证方法包括将要验证的布局数据加载到处理器，将参考布局数据加载到处理器。 处理器对待验证的布局数据执行第一阶段布尔运算以生成第一验证数据。 处理器通过使用数据库中的光学邻近校正数据的用户定义的验证工具对第一验证数据执行布局与布局验证，以根据参考布局数据生成第二验证数据。 如果成功执行布局对布局验证，则处理器对第二验证数据执行第二阶段布尔运算以产生第三验证数据。 处理器对第三个验证数据执行布尔检查，以使用参考布局数据生成第四个验证数据。

公开(公告)号：US09323883B2

公开(公告)日：2016-04-26

申请号：US14337187

申请日：2014-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chao-Yao Chiang ,  Kuo-Hsun Huang ,  Chien-Hung Chen

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5068

Abstract: A planar design to non-planar design conversion method includes following steps. At least a diffusion region pattern including a first side and a second side perpendicular to each other is received. A look-up table is queried to obtain a first positive integer according to the first side of the diffusion region pattern and a second positive integer according to the second side of the diffusion region pattern. Then, a plurality of fin patterns is formed. An amount of the fin patterns is equal to the second positive integer. The fin patterns respectively include a first fin length, and the first fin length is a product of the first positive integer and a predetermined value. The forming is performed by at least a computer-aided design (CAD) tool.

Abstract translation: 非平面设计转换方法的平面设计包括以下步骤。 至少包括彼此垂直的第一侧和第二侧的扩散区图案。 查询表根据扩散区域图案的第一侧获得第一正整数，并根据扩散区图案的第二侧获得第二正整数。 然后，形成多个翅片图案。 鳍图案的数量等于第二正整数。 翅片图案分别包括第一翅片长度，并且第一翅片长度是第一正整数和预定值的乘积。 至少由计算机辅助设计（CAD）工具进行成型。

公开(公告)号：US20160004806A1

公开(公告)日：2016-01-07

申请号：US14324231

申请日：2014-07-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsun Huang ,  Hsi-Chang Chang ,  Chao-Yao Chiang ,  Chien-Hung Chen

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/504 ,  G06F17/5081

Abstract: A computer implemented method for performing extraction is provided in the present invention. First, a layout of a semiconductor circuit having a resistor is imported by using a computer wherein a device region is defined in the layout and the resistor is located within the device region. Next, the device region of the layout are extracted, and a compensation value of Rs (Rc) is obtained according to the extracting step. An adjustment process is performed according to Rc to obtained a refined R value.

Abstract translation: 本发明提供了一种用于执行提取的计算机实现方法。 首先，通过使用其中在布局中限定器件区域并且电阻器位于器件区域内的计算机来导入具有电阻器的半导体电路的布局。 接下来，提取布局的设备区域，并且根据提取步骤获得Rs（Rc）的补偿值。 根据Rc执行调整处理以获得精确的R值。