公开(公告)号：US09379242B1

公开(公告)日：2016-06-28

申请号：US14723476

申请日：2015-05-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Mon-Sen Lin ,  Yu-Ping Wang ,  Yu-Ting Tseng ,  Hao-Yeh Liu ,  Chun-tsen Lu

IPC: H01L21/4763 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L27/088 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L29/7847 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of fabricating a fin field effect transistor including providing a substrate having at least one fin structure, a dummy gate, and an internal dielectric layer thereon, removing the dummy gate to form a gate trench on the fin structure, blanketly forming a stress film on the substrate to cover a surface of the gate trench, performing a thermal annealing process, removing the stress film, and forming a metal gate is in the gate trench.

Abstract translation: 一种制造鳍状场效应晶体管的方法，包括：在其上提供具有至少一个鳍结构的衬底，伪栅极和内部电介质层，去除所述虚设栅极以在所述鳍结构上形成栅极沟槽，以覆盖形式施加应力膜 在基板上覆盖栅极沟槽的表面，执行热退火处理，去除应力膜和形成金属栅极在栅极沟槽中。

公开(公告)号：US20150004780A1

公开(公告)日：2015-01-01

申请号：US14490679

申请日：2014-09-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsun-Min Cheng ,  Min-Chuan Tsai ,  Chih-Chien Liu ,  Jen-Chieh Lin ,  Pei-Ying Li ,  Shao-Wei Wang ,  Mon-Sen Lin ,  Ching-Ling Lin

IPC: H01L29/49 ,  H01L21/8234

CPC classification number: H01L29/4966 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4232 ,  H01L29/435 ,  H01L29/51 ,  H01L29/66045 ,  H01L29/66545 ,  H01L29/78

Abstract: A metal gate structure located on a substrate includes a gate dielectric layer, a metal layer and a titanium aluminum nitride metal layer. The gate dielectric layer is located on the substrate. The metal layer is located on the gate dielectric layer. The titanium aluminum nitride metal layer is located on the metal layer.

Abstract translation: 位于基板上的金属栅极结构包括栅介质层，金属层和氮化铝钛金属层。 栅介质层位于衬底上。 金属层位于栅极电介质层上。 氮化铝钛金属层位于金属层上。

公开(公告)号：US09524967B1

公开(公告)日：2016-12-20

申请号：US15046458

申请日：2016-02-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao-Yeh Liu ,  Chien-Ming Lai ,  Yu-Ping Wang ,  Mon-Sen Lin ,  Ya-Huei Tsai ,  Ching-Hsiang Chiu

IPC: H01L27/088 ,  H01L27/092 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/092

Abstract: A semiconductor device and a method of forming the same, the semiconductor device include a substrate, and a first transistor, a second transistor and a third transistor all disposed on the substrate. The first transistor includes a first channel, and a first barrier layer and a first work function layer stacked with each other on the first channel. The second transistor includes a second channel, and a second barrier layer and a second work function layer stacked with each other. The third transistor includes a third channel and a third barrier layer and a third work function layer stacked with each other on the third channel, wherein the first barrier layer, the second barrier layer and the third barrier layer have different nitrogen ratio. The first, the second and the third transistors have different threshold voltages, respectively.

Abstract translation: 半导体器件及其形成方法，所述半导体器件包括基板，以及全部设置在所述基板上的第一晶体管，第二晶体管和第三晶体管。 第一晶体管包括第一通道，以及在第一通道上彼此堆叠的第一势垒层和第一功函数层。 第二晶体管包括第二通道，以及彼此堆叠的第二阻挡层和第二功能层。 第三晶体管包括在第三沟道上彼此堆叠的第三沟道和第三势垒层和第三功函数层，其中第一势垒层，第二阻挡层和第三势垒层具有不同的氮比。 第一，第二和第三晶体管分别具有不同的阈值电压。

公开(公告)号：US09281374B2

公开(公告)日：2016-03-08

申请号：US14490679

申请日：2014-09-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsun-Min Cheng ,  Min-Chuan Tsai ,  Chih-Chien Liu ,  Jen-Chieh Lin ,  Pei-Ying Li ,  Shao-Wei Wang ,  Mon-Sen Lin ,  Ching-Ling Lin

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/43 ,  H01L29/772 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L29/4966 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4232 ,  H01L29/435 ,  H01L29/51 ,  H01L29/66045 ,  H01L29/66545 ,  H01L29/78

Abstract: A metal gate structure located on a substrate includes a gate dielectric layer, a metal layer and a titanium aluminum nitride metal layer. The gate dielectric layer is located on the substrate. The metal layer is located on the gate dielectric layer. The titanium aluminum nitride metal layer is located on the metal layer.

Abstract translation: 位于基板上的金属栅极结构包括栅介质层，金属层和氮化铝钛金属层。 栅介质层位于衬底上。 金属层位于栅极电介质层上。 氮化铝钛金属层位于金属层上。