公开(公告)号：US12237398B2

公开(公告)日：2025-02-25

申请号：US17338691

申请日：2021-06-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ming Kuo ,  Po-Jen Chuang ,  Yu-Ren Wang ,  Ying-Wei Yen ,  Fu-Jung Chuang ,  Ya-Yin Hsiao ,  Nan-Yuan Huang

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/28 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/324 ,  H01L29/08 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/423

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer adjacent to the gate structure, wherein the first spacer comprises silicon carbon nitride (SiCN); forming a second spacer adjacent to the first spacer, wherein the second spacer comprises silicon oxycarbonitride (SiOCN); and forming a source/drain region adjacent to two sides of the second spacer.

公开(公告)号：US20240421213A1

公开(公告)日：2024-12-19

申请号：US18813074

申请日：2024-08-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Jung Chuang ,  Tsuo-Wen Lu ,  Chia-Ming Kuo ,  Po-Jen Chuang ,  Chi-Mao Hsu

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L29/78

Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on sidewalls of gate structure, a second spacer on sidewalls of the first spacer, a polymer block adjacent to the first spacer and on a corner between the gate structure and the substrate, an interfacial layer under the polymer block, and a source/drain region adjacent to two sides of the first spacer. Preferably, the polymer block is surrounded by the first spacer, the interfacial layer, and the second spacer.

公开(公告)号：US11508832B2

公开(公告)日：2022-11-22

申请号：US17209244

申请日：2021-03-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Jung Chuang ,  Tsuo-Wen Lu ,  Chia-Ming Kuo ,  Po-Jen Chuang ,  Chi-Mao Hsu

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L21/311

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a polymer block on a corner between the gate structure and the substrate; performing a cleaning process; performing an oxidation process by injecting oxygen gas under 750° C. to form a first seal layer on sidewalls of the gate structure; and forming a source/drain region adjacent to two sides of the gate structure.

公开(公告)号：US20210296466A1

公开(公告)日：2021-09-23

申请号：US17338691

申请日：2021-06-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ming Kuo ,  Po-Jen Chuang ,  Yu-Ren Wang ,  Ying-Wei Yen ,  Fu-Jung Chuang ,  Ya-Yin Hsiao ,  Nan-Yuan Huang

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324 ,  H01L29/08 ,  H01L29/78

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer adjacent to the gate structure, wherein the first spacer comprises silicon carbon nitride (SiCN); forming a second spacer adjacent to the first spacer, wherein the second spacer comprises silicon oxycarbonitride (SiOCN); and forming a source/drain region adjacent to two sides of the second spacer.

公开(公告)号：US10475709B1

公开(公告)日：2019-11-12

申请号：US16030871

申请日：2018-07-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Jung Chuang ,  Ching-Ling Lin ,  Po-Jen Chuang ,  Yu-Ren Wang ,  Wen-An Liang ,  Chia-Ming Kuo ,  Guan-Wei Huang ,  Yuan-Yu Chung ,  I-Ming Tseng

IPC: H01L21/00 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/762

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; removing part of the first fin-shaped structure to forma first trench; forming a dielectric layer in the first trench, wherein the dielectric layer comprises silicon oxycarbonitride (SiOCN); and planarizing the dielectric layer to form a first single diffusion break (SDB) structure.

公开(公告)号：US09882022B2

公开(公告)日：2018-01-30

申请号：US15592150

申请日：2017-05-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ming Kuo ,  Po-Jen Chuang ,  Fu-Jung Chuang ,  Tsai-Yu Wen ,  Tsuo-Wen Lu ,  Yu-Ren Wang ,  Fu-Yu Tsai

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28 ,  H01L29/49 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0228 ,  H01L21/28088 ,  H01L21/31111 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device and a method for manufacturing the same are provided in the present invention. The semiconductor device includes a substrate, a gate structure on the substrate and two spacers on both sidewalls of the gate structure. Each spacer comprises an inner first spacer portion made of SiCN and an outer second spacer portion made of SiOCN.

公开(公告)号：US12057401B2

公开(公告)日：2024-08-06

申请号：US18226784

申请日：2023-07-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Cheng Chen ,  Li-Hsuan Ho ,  Tsuo-Wen Lu ,  Shih-Hao Liang ,  Tsung-Hsun Wu ,  Po-Jen Chuang ,  Chi-Mao Hsu

IPC: H01L23/535 ,  H01L21/28 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L23/535 ,  H01L21/28088 ,  H01L21/82385 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/66545

Abstract: A semiconductor device including a substrate having a NMOS region and a PMOS region; a metal gate extending continuously along a first direction from the NMOS region to the PMOS region on the substrate; a first source/drain region extending along a second direction adjacent to two sides of the metal gate on the NMOS region; a second source/drain region extending along the second direction adjacent to two sides of the metal gate on the PMOS region; a first contact plug landing on the second source/drain region adjacent to one side of the metal gate; a second contact plug landing on the second source/drain region adjacent to another side of the metal gate; and a third contact plug landing directly on a portion of the metal gate on the PMOS region and between the first contact plug and the second contact plug.

公开(公告)号：US20230386939A1

公开(公告)日：2023-11-30

申请号：US18233331

申请日：2023-08-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Jung Chuang ,  Po-Jen Chuang ,  Yu-Ren Wang ,  Chi-Mao Hsu ,  Chia-Ming Kuo ,  Guan-Wei Huang ,  Chun-Hsien Lin

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/762

CPC classification number: H01L21/823878 ,  H01L27/0924 ,  H01L21/76224 ,  H01L21/823821

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the first fin-shaped structure into a first portion and a second portion, and more than two gate structures on the SDB structure. Preferably, the more than two gate structures include a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure disposed on the SDB structure.

公开(公告)号：US20230327000A1

公开(公告)日：2023-10-12

申请号：US18208895

申请日：2023-06-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Jung Chuang ,  Tsuo-Wen Lu ,  Chia-Ming Kuo ,  Po-Jen Chuang ,  Chi-Mao Hsu

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L29/66795 ,  H01L29/66545 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L29/785 ,  H01L21/31116

Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on sidewalls of gate structure, a second spacer on sidewalls of the first spacer, a polymer block adjacent to the first spacer and on a corner between the gate structure and the substrate, an interfacial layer under the polymer block, and a source/drain region adjacent to two sides of the first spacer. Preferably, the polymer block is surrounded by the first spacer, the interfacial layer, and the second spacer.

公开(公告)号：US11271090B2

公开(公告)日：2022-03-08

申请号：US16867579

申请日：2020-05-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ming Kuo ,  Fu-Jung Chuang ,  Po-Jen Chuang ,  Chia-Wei Chang ,  Guan-Wei Huang ,  Chia-Yuan Chang

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/265

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a first gate structure on the NMOS region and a second gate structure on the PMOS region; forming a seal layer on the first gate structure and the second gate structure; forming a first lightly doped drain (LDD) adjacent to the first gate structure; forming a second LDD adjacent to the second gate structure; and performing a soak anneal process to boost an oxygen concentration of the seal layer for reaching a saturation level.