公开(公告)号：US20240304657A1

公开(公告)日：2024-09-12

申请号：US18128218

申请日：2023-03-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Chun Teng ,  Ming-Che Tsai ,  Ping-Chia Shih ,  Yi-Chang Huang ,  Wen-Lin Wang ,  Yu-Fan Hu ,  Ssu-Yin Liu ,  Yu-Nong Chen ,  Pei-Tsen Shiu ,  Cheng-Tzung Tsai

IPC: H01L27/06

CPC classification number: H01L28/24 ,  H01L27/0629

Abstract: A semiconductor device includes a substrate, a first gate, a plurality of second gates and a resistor. The substrate is defined with an active region and a resistor region. The first gate is disposed in the active region. The first gate has a first length extending along a first direction and a second length extending along a second direction. The plurality of second gates are disposed in the resistor region. Each of the second gates has a third length extending along the first direction and a fourth length extending along the second direction. The first length is equal to the third length, and the second length is equal to the fourth length. The resistor is disposed on the plurality of second gates.

公开(公告)号：US11616069B2

公开(公告)日：2023-03-28

申请号：US17073443

申请日：2020-10-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ping-Chia Shih ,  Kuei-Ya Chuang ,  Chuang-Hsin Chueh ,  Ming-Che Tsai ,  Wen-Lin Wang ,  Yi-Chun Teng ,  Ssu-Yin Liu ,  Wan-Chun Liao

IPC: H01L27/11521

Abstract: The present application discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, a gate dielectric layer, a floating gate, a first dielectric layer and a control gate. The gate dielectric layer is disposed on the substrate. The floating gate is disposed on the gate dielectric layer and has at least one tip on a top surface of the floating gate. The first dielectric layer is disposed on the floating gate. The control gate is disposed above the first dielectric layer and at least partially overlaps the floating gate.

公开(公告)号：US20220293615A1

公开(公告)日：2022-09-15

申请号：US17198268

申请日：2021-03-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Min Hung ,  Ping-Chia Shih ,  Che-Hao Kuo ,  Kuei-Ya Chuang ,  Ssu-Yin Liu ,  Po-Hsien Chen ,  Wan-Chun Liao

IPC: H01L27/11521 ,  H01L29/423 ,  H01L29/788 ,  H01L21/28 ,  H01L29/66

Abstract: A method of forming a flash memory cell includes the following steps. A first dielectric layer and a floating gate layer are deposited on a substrate sequentially. Three blocking structures having oblique sidewalls broaden from bottom to top penetrating through the first dielectric layer and the floating gate layer are formed. A first part and a second part of the floating gate layer between two adjacent blocking structures are etched respectively, so that a first floating gate having two sharp top corners and oblique sidewalls, and a second floating gate having two sharp top corners and oblique sidewalls, are formed. The three blocking structures are removed. A first isolating layer and a first selective gate covering the first floating gate are formed and a second isolating layer and a second selective gate covering the second floating gate are formed. A flash memory cell formed by said method is also provided.

公开(公告)号：US11758720B2

公开(公告)日：2023-09-12

申请号：US18077183

申请日：2022-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Min Hung ,  Ping-Chia Shih ,  Che-Hao Kuo ,  Kuei-Ya Chuang ,  Ssu-Yin Liu ,  Po-Hsien Chen ,  Wan-Chun Liao

IPC: H10B41/30 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/788

CPC classification number: H10B41/30 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method of forming a flash memory cell includes the following steps. A first dielectric layer and a floating gate layer are deposited on a substrate sequentially. Three blocking structures having oblique sidewalls broaden from bottom to top penetrating through the first dielectric layer and the floating gate layer are formed. A first part and a second part of the floating gate layer between two adjacent blocking structures are etched respectively, so that a first floating gate having two sharp top corners and oblique sidewalls, and a second floating gate having two sharp top corners and oblique sidewalls, are formed. The three blocking structures are removed. A first isolating layer and a first selective gate covering the first floating gate are formed and a second isolating layer and a second selective gate covering the second floating gate are formed. A flash memory cell formed by said method is also provided.

公开(公告)号：US20230260827A1

公开(公告)日：2023-08-17

申请号：US17687692

申请日：2022-03-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ping-Chia Shih ,  Che-Hao Kuo ,  Ssu-Yin Liu ,  Ching-Hua Yeh ,  I-Hsin Sung

IPC: H01L21/762 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/3115 ,  H01L23/00

CPC classification number: H01L21/76224 ,  H01L21/32139 ,  H01L21/31144 ,  H01L21/31155 ,  H01L23/573

Abstract: A method for fabricating a physically unclonable function (PUF) device includes the steps of first defining a PUF cell region on a substrate and then performing a process to form a defect on the PUF cell region. Preferably, the formation of the defect could be accomplished by forming a shallow trench isolation (STI) on the substrate, forming a gate material layer on the substrate and the STI, patterning the gate material layer to form a first gate material layer and a second gate material layer, and then forming an epitaxial layer between and connecting the first gate material layer and the second gate material layer.

公开(公告)号：US11552088B2

公开(公告)日：2023-01-10

申请号：US17198268

申请日：2021-03-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Min Hung ,  Ping-Chia Shih ,  Che-Hao Kuo ,  Kuei-Ya Chuang ,  Ssu-Yin Liu ,  Po-Hsien Chen ,  Wan-Chun Liao

IPC: H01L27/11521 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/788

Abstract: A method of forming a flash memory cell includes the following steps. A first dielectric layer and a floating gate layer are deposited on a substrate sequentially. Three blocking structures having oblique sidewalls broaden from bottom to top penetrating through the first dielectric layer and the floating gate layer are formed. A first part and a second part of the floating gate layer between two adjacent blocking structures are etched respectively, so that a first floating gate having two sharp top corners and oblique sidewalls, and a second floating gate having two sharp top corners and oblique sidewalls, are formed. The three blocking structures are removed. A first isolating layer and a first selective gate covering the first floating gate are formed and a second isolating layer and a second selective gate covering the second floating gate are formed. A flash memory cell formed by said method is also provided.