公开(公告)号：US20220302118A1

公开(公告)日：2022-09-22

申请号：US17230975

申请日：2021-04-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Kun-Hsien Lee ,  Sheng-Yuan Hsueh ,  Chang-Chien Wong ,  Ching-Hsiang Tseng ,  Tsung-Hsun Wu ,  Chi-Horn Pai ,  Shih-Chieh Hsu

IPC: H01L27/108

Abstract: The invention provides a semiconductor memory cell, the semiconductor memory cell includes a substrate having a first conductivity type, a doped region in the substrate, wherein the doped region has a second conductivity type, and the first conductivity type is complementary to the second conductivity type, a capacitor insulating layer and an upper electrode on the doped region, a transistor on the substrate, and a shallow trench isolation disposed between the transistor and the capacitor insulating layer, and the shallow trench isolation is disposed in the doped region.

公开(公告)号：US11171091B2

公开(公告)日：2021-11-09

申请号：US16695028

申请日：2019-11-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Cheng Chen ,  Li-Hsuan Ho ,  Tsuo-Wen Lu ,  Shih-Hao Liang ,  Tsung-Hsun Wu ,  Po-Jen Chuang ,  Chi-Mao Hsu

IPC: H01L23/535 ,  H01L27/092 ,  H01L23/528 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/28 ,  H01L29/49

Abstract: A semiconductor device includes a substrate having a NMOS region and a PMOS region; a gate structure extending along a first direction from the NMOS region to the PMOS region on the substrate; and a first contact plug landing directly on the gate structure closer to the PMOS region from a boundary separating the NMOS region and the PMOS region. Preferably, the semiconductor device further includes a first source/drain region extending along a second direction adjacent to two sides of the gate structure on the NMOS region and a second source/drain region extending along the second direction adjacent to two sides of the gate structure on the PMOS region.

公开(公告)号：US20210125927A1

公开(公告)日：2021-04-29

申请号：US16695028

申请日：2019-11-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Cheng Chen ,  Li-Hsuan Ho ,  Tsuo-Wen Lu ,  Shih-Hao Liang ,  Tsung-Hsun Wu ,  Po-Jen Chuang ,  Chi-Mao Hsu

IPC: H01L23/535 ,  H01L27/092 ,  H01L23/528 ,  H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate having a NMOS region and a PMOS region; a gate structure extending along a first direction from the NMOS region to the PMOS region on the substrate; and a first contact plug landing directly on the gate structure closer to the PMOS region from a boundary separating the NMOS region and the PMOS region. Preferably, the semiconductor device further includes a first source/drain region extending along a second direction adjacent to two sides of the gate structure on the NMOS region and a second source/drain region extending along the second direction adjacent to two sides of the gate structure on the PMOS region.

公开(公告)号：US10529723B2

公开(公告)日：2020-01-07

申请号：US15186548

申请日：2016-06-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shu-Wei Yeh ,  Tsung-Hsun Wu ,  Chih-Ming Su ,  Yu-Tse Kuo

IPC: H01L27/11 ,  H01L27/02

Abstract: A layout pattern of a static random access memory includes a pull-up device, a first pull-down device, a second pull-up device, a second pull-down device, a first pass gate device and a second pass gate device disposed on a substrate. A plurality of fin structures are disposed on the substrate, and the fin structures include at least one first fin structure and at least one second fin structure. A J-shaped gate structure is disposed on the substrate, including a long part, a short part and a bridge part. At least one first extending contact structure crosses over the at least one first fin structure and the at least one second fin structure, wherein the at least one first extending contact structure does not overlap with the bridge part of the J-shaped gate structure.

公开(公告)号：US20170323894A1

公开(公告)日：2017-11-09

申请号：US15186548

申请日：2016-06-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shu-Wei Yeh ,  Tsung-Hsun Wu ,  Chih-Ming Su ,  Yu-Tse Kuo

IPC: H01L27/11 ,  H01L29/10 ,  H01L27/088 ,  H01L27/02 ,  H01L23/532 ,  H01L29/423 ,  H01L23/528

CPC classification number: H01L27/1104 ,  G11C8/14 ,  G11C11/412 ,  G11C11/418 ,  G11C14/0054 ,  H01L27/0207 ,  H01L27/0924

Abstract: A layout pattern of a static random access memory includes a pull-up device, a first pull-down device, a second pull-up device, a second pull-down device, a first pass gate device and a second pass gate device disposed on a substrate. A plurality of fin structures are disposed on the substrate, and the fin structures include at least one first fin structure and at least one second fin structure. A J-shaped gate structure is disposed on the substrate, including a long part, a short part and a bridge part. At least one first extending contact structure crosses over the at least one first fin structure and the at least one second fin structure, wherein the at least one first extending contact structure does not overlap with the bridge part of the J-shaped gate structure.

公开(公告)号：US20250142799A1

公开(公告)日：2025-05-01

申请号：US18398227

申请日：2023-12-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yen Tseng ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Tsung-Hsun Wu ,  Liang-Wei Chiu ,  Chun-Hsien Huang

IPC: H10B10/00

Abstract: The invention provides a layout pattern of static random-access memory (SRAM), which comprises a substrate, wherein a plurality of diffusion regions and a plurality of gate structures are located on the substrate to form a plurality of transistors, wherein the plurality of gate structures comprise a first gate structure, which has a stepped shape when viewed from a top view, and the first gate structure spans a first diffusion region and a second diffusion region to form a first access transistor (PG1), wherein the first diffusion region is adjacent to and in direct contact with the second diffusion region.

公开(公告)号：US20240363539A1

公开(公告)日：2024-10-31

申请号：US18764355

申请日：2024-07-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Cheng Chen ,  Li-Hsuan Ho ,  Tsuo-Wen Lu ,  Shih-Hao Liang ,  Tsung-Hsun Wu ,  Po-Jen Chuang ,  Chi-Mao Hsu

IPC: H01L23/535 ,  H01L21/28 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L23/535 ,  H01L21/28088 ,  H01L21/82385 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/66545

Abstract: A semiconductor device including a substrate having a NMOS region and a PMOS region; a metal gate extending continuously along a first direction from the NMOS region to the PMOS region on the substrate; a first source/drain region extending along a second direction adjacent to two sides of the metal gate on the NMOS region; a second source/drain region extending along the second direction adjacent to two sides of the metal gate on the PMOS region; a first contact plug landing on the second source/drain region adjacent to one side of the metal gate; a second contact plug landing on the second source/drain region adjacent to another side of the metal gate; and a third contact plug landing directly on a portion of the metal gate on the PMOS region and between the first contact plug and the second contact plug.

公开(公告)号：US20240144994A1

公开(公告)日：2024-05-02

申请号：US18070484

申请日：2022-11-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hsiu Wu ,  Tsung-Hsun Wu

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4094

CPC classification number: G11C11/4096 ,  G11C11/4085 ,  G11C11/4094

Abstract: A random access memory, including a write transistor with a gate electrically connected to a write word line and a drain electrically connected to a write bit line, a first read transistor and a second read transistor with gates electrically connected to a source of the write transistor to form a storage node, drains electrically connected to a read bit line and a common source electrically connected to a read word line so that the first read transistor and a second read transistor are in parallel connection, and a capacitor electrically connected to the storage node.

公开(公告)号：US20180006038A1

公开(公告)日：2018-01-04

申请号：US15682558

申请日：2017-08-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shu-Wei Yeh ,  Tsung-Hsun Wu ,  Chih-Ming Su ,  Zhi-Xian Chou

IPC: H01L27/11 ,  G11C11/412 ,  H01L27/02 ,  H01L29/78

CPC classification number: H01L27/1104 ,  G11C11/412 ,  H01L27/0207 ,  H01L28/00 ,  H01L29/785

Abstract: A layout pattern of a static random access memory includes a pull-up device, a first pull-down device, a second pull-up device, a second pull-down device, a first pass gate device, a second pass gate device, a third pass gate device and a fourth pass gate device disposed on a substrate. A plurality of fin structures is disposed on the substrate, the fin structures including at least one first fin structure and at least one second fin structure. A step-shaped structure is disposed on the substrate, including a first part, a second part and a bridge part. A first extending contact feature crosses over the at least one first fin structure and the at least one second fin structure.

公开(公告)号：US09780099B1

公开(公告)日：2017-10-03

申请号：US15233961

申请日：2016-08-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shu-Wei Yeh ,  Tsung-Hsun Wu ,  Chih-Ming Su ,  Zhi-Xian Chou

IPC: G11C11/04 ,  H01L27/11 ,  H01L29/78 ,  H01L27/02 ,  G11C11/412

CPC classification number: H01L27/1104 ,  G11C11/412 ,  H01L27/0207 ,  H01L28/00 ,  H01L29/785

Abstract: A layout pattern of a static random access memory includes a pull-up device, a first pull-down device, a second pull-up device, a second pull-down device, a first pass gate device, a second pass gate device, a third pass gate device and a fourth pass gate device disposed on a substrate. A plurality of fin structures is disposed on the substrate, the fin structures including at least one first fin structure and at least one second fin structure. A step-shaped structure is disposed on the substrate, including a first part, a second part and a bridge part. A first extending contact feature crosses over the at least one first fin structure and the at least one second fin structure.