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公开(公告)号：US12063792B2
公开(公告)日：2024-08-13
申请号：US18207654
申请日：2023-06-08
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Po-Kai Hsu , Jing-Yin Jhang , Yu-Ping Wang , Hung-Yueh Chen , Wei Chen
Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming a first metal interconnection adjacent to the MTJ; forming a stop layer on the first IMD layer; removing the stop layer to form an opening; and forming a channel layer in the opening to electrically connect the MTJ and the first metal interconnection.
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公开(公告)号：US20240196756A1
公开(公告)日：2024-06-13
申请号：US18587823
申请日：2024-02-26
Applicant: United Microelectronics Corp.
Inventor： Hui-Lin Wang , Wei Chen , Po-Kai Hsu , Yu-Ping Wang , Hung-Yueh Chen
CPC classification number: H10N50/01 , H01F10/3254 , H01F10/329 , H10N50/80
Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection and a second metal interconnection in the first IMD layer; forming a channel layer on the first metal interconnection and the second metal interconnection; forming a magnetic tunneling junction (MTJ) stack on the channel layer; and removing the MTJ stack to form a MTJ.
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公开(公告)号：US10943948B2
公开(公告)日：2021-03-09
申请号：US16261584
申请日：2019-01-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wei Chen , Hui-Lin Wang , Yu-Ru Yang , Chin-Fu Lin , Yi-Syun Chou , Chun-Yao Yang
Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.
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公开(公告)号：US20240365563A1
公开(公告)日：2024-10-31
申请号：US18762663
申请日：2024-07-03
Applicant: UNITED MICROELECTRONICS CORP
Inventor： Hui-Lin Wang , Po-Kai Hsu , Jing-Yin Jhang , Yu-Ping Wang , Hung-Yueh Chen , Wei Chen
Abstract: A semiconductor device including a magnetic tunneling junction (MTJ) and a hard mask on a substrate, a first inter-metal dielectric (IMD) layer around the MTJ, a first metal interconnection adjacent to the MTJ, a first barrier layer and a channel layer on the first IMD layer to directly contact the hard mask and electrically connect the MTJ and the first metal interconnection, and a stop layer around the channel layer.
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公开(公告)号：US11856870B2
公开(公告)日：2023-12-26
申请号：US17844741
申请日：2022-06-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Kuo-Chih Lai , Yi-Syun Chou , Ko-Wei Lin , Pei-Hsun Kao , Wei Chen , Chia-Fu Cheng , Chun-Yao Yang , Chia-Chang Hsu
Abstract: A magnetoresistive random access memory (MRAM) structure includes a magnetic tunnel junction (MTJ), and a top electrode which contacts an end of the MTJ. The top electrode includes a top electrode upper portion and a top electrode lower portion. The width of the top electrode upper portion is larger than the width of the top electrode lower portion. A bottom electrode contacts another end of the MTJ. The top electrode, the MTJ and the bottom electrode form an MRAM.
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Patent Agency Ranking
公开(公告)号：US20230329006A1
公开(公告)日：2023-10-12
申请号：US18207654
申请日：2023-06-08
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Po-Kai Hsu , Jing-Yin Jhang , Yu-Ping Wang , Hung-Yueh Chen , Wei Chen
Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming a first metal interconnection adjacent to the MTJ; forming a stop layer on the first IMD layer; removing the stop layer to form an opening; and forming a channel layer in the opening to electrically connect the MTJ and the first metal interconnection.
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公开(公告)号：US11716860B2
公开(公告)日：2023-08-01
申请号：US16882783
申请日：2020-05-26
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Po-Kai Hsu , Jing-Yin Jhang , Yu-Ping Wang , Hung-Yueh Chen , Wei Chen
Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming a first metal interconnection adjacent to the MTJ; forming a stop layer on the first IMD layer; removing the stop layer to form an opening; and forming a channel layer in the opening to electrically connect the MTJ and the first metal interconnection.
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公开(公告)号：US10756128B2
公开(公告)日：2020-08-25
申请号：US16244109
申请日：2019-01-10
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Kuo-Chih Lai , Shih-Min Chou , Ko-Wei Lin , Chin-Fu Lin , Wei-Chuan Tsai , Chun-Yao Yang , Chia-Fu Cheng , Yi-Syun Chou , Wei Chen
IPC: H01L27/14 , H01L27/146 , H01L21/768 , H01L49/02
Abstract: An integrated circuit device includes a complementary metal oxide semiconductor (CMOS) image sensor. The complementary metal oxide semiconductor (CMOS) image sensor includes a P-N junction photodiode, a transistor gate, a polysilicon plug and a stacked metal layer. The P-N junction photodiode is disposed in a substrate. The transistor gate and the polysilicon plug are disposed on the substrate, wherein the polysilicon plug is directly connected to the P-N junction photodiode. The stacked metal layer connects the polysilicon plug to the transistor gate, wherein the stacked metal layer includes a lower metal layer and an upper metal layer, and the lower metal layer includes a first metal silicide part contacting to the polysilicon plug. The present invention also provides a method of fabricating said integrated circuit device.
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公开(公告)号：US20200212090A1
公开(公告)日：2020-07-02
申请号：US16244109
申请日：2019-01-10
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Kuo-Chih Lai , Shih-Min Chou , Ko-Wei Lin , Chin-Fu Lin , Wei-Chuan Tsai , Chun-Yao Yang , Chia-Fu Cheng , Yi-Syun Chou , Wei Chen
IPC: H01L27/146 , H01L49/02 , H01L21/768
Abstract: An integrated circuit device includes a complementary metal oxide semiconductor (CMOS) image sensor. The complementary metal oxide semiconductor (CMOS) image sensor includes a P-N junction photodiode, a transistor gate, a polysilicon plug and a stacked metal layer. The P-N junction photodiode is disposed in a substrate. The transistor gate and the polysilicon plug are disposed on the substrate, wherein the polysilicon plug is directly connected to the P-N junction photodiode. The stacked metal layer connects the polysilicon plug to the transistor gate, wherein the stacked metal layer includes a lower metal layer and an upper metal layer, and the lower metal layer includes a first metal silicide part contacting to the polysilicon plug. The present invention also provides a method of fabricating said integrated circuit device.
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公开(公告)号：US11950513B2
公开(公告)日：2024-04-02
申请号：US17857185
申请日：2022-07-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Wei Chen , Po-Kai Hsu , Yu-Ping Wang , Hung-Yueh Chen
CPC classification number: H10N50/01 , H01F10/3254 , H01F10/329 , H10N50/80
Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection and a second metal interconnection in the first IMD layer; forming a channel layer on the first metal interconnection and the second metal interconnection; forming a magnetic tunneling junction (MTJ) stack on the channel layer; and removing the MTJ stack to form a MTJ.
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