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公开(公告)号：US12193345B2
公开(公告)日：2025-01-07
申请号：US18503140
申请日：2023-11-06
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wen-Jen Wang , Chun-Hung Cheng , Chuan-Fu Wang
Abstract: A resistive random access memory (RRAM) structure includes a RRAM cell, spacers and a dielectric layer. The RRAM cell is disposed on a substrate. The spacers are disposed beside the RRAM cell, wherein widths of top surfaces of the spacers are larger than or equal to widths of bottom surfaces of the spacers. The dielectric layer blanketly covers the substrate and sandwiches the RRAM cell, wherein the spacers are located in the dielectric layer. A method for forming the resistive random access memory (RRAM) structure is also provided.
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公开(公告)号：US20240188306A1
公开(公告)日：2024-06-06
申请号：US18096532
申请日：2023-01-12
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wen-Jen Wang , Yu-Huan Yeh , Chuan-Fu Wang , Hsiang-Hung Peng
IPC: H10B63/00
CPC classification number: H10B63/82
Abstract: A resistive memory device includes a dielectric layer, a first via connection structure, a first stacked structure, and a first insulating structure. The first via connection structure is disposed in the dielectric layer. The first stacked structure is disposed on the first via connection structure and the dielectric layer. The first insulating structure penetrates through a portion of the first stacked structure in a vertical direction and divides the first stacked structure into a first cell unit and a second cell unit. The first cell unit and the second cell unit include a first shared bottom electrode, and the first insulating structure is disposed directly on the first shared bottom electrode.
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公开(公告)号：US11871685B2
公开(公告)日：2024-01-09
申请号：US17378795
申请日：2021-07-19
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wen-Jen Wang , Chun-Hung Cheng , Chuan-Fu Wang
CPC classification number: H10N70/841 , H10N70/011 , H10N70/24 , H10N70/826 , H10N70/8833
Abstract: A RRAM device includes a bottom electrode, a resistive material layer, a high work function layer, a top electrode, a hard mask and high work function sidewall parts. The bottom electrode, the resistive material layer, the high work function layer, the top electrode and the hard mask are sequentially stacked on a substrate. The high work function sidewall parts cover sidewalls of the top electrode and sidewalls of the hard mask, thereby constituting a RRAM cell. A method of forming said RRAM device is also provided.
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公开(公告)号：US20230354724A1
公开(公告)日：2023-11-02
申请号：US17750425
申请日：2022-05-23
Applicant: United Microelectronics Corp.
Inventor： Wen-Jen Wang , Chun-Hung Cheng , Chuan-Fu Wang
CPC classification number: H01L45/1253 , H01L45/146 , H01L28/24 , H01L45/1625 , H01L45/1616
Abstract: Provided is a resistive memory structure and a manufacturing method thereof. The resistive memory structure includes a substrate, a dielectric layer, a resistive memory device, a hard mask layer, and a spacer. The dielectric layer is located on the substrate. The dielectric layer has an opening. The resistive memory device is located in the opening and has a protrusion outside the opening. The resistive memory device includes a first electrode, a variable resistance layer, and a second electrode. The variable resistance layer is located on the first electrode. The second electrode is located on the variable resistance layer. The hard mask layer covers a top surface of the variable resistance layer. The spacer covers a sidewall of the variable resistance layer in the protrusion.
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公开(公告)号：US11765915B2
公开(公告)日：2023-09-19
申请号：US17870814
申请日：2022-07-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wen-Jen Wang , Chun-Hung Cheng , Chuan-Fu Wang
CPC classification number: H10B63/80 , H10N70/063 , H10N70/826
Abstract: A semiconductor device includes a substrate having a memory region and a logic region. A first dielectric layer is disposed on the substrate. A first conductive structure and a second conductive structure are respectively formed in the first dielectric layer on the memory region and the logic region. A memory cell is formed on the first dielectric layer and directly contacts a top surface of the first conductive structure. A first cap layer continuously covers a top surface and a sidewall of the memory cell and directly contacts a top surface of the second conductive structure. A second dielectric layer is formed on the first cap layer. A third conductive structure penetrates through the second dielectric layer and the first cap layer to contact the memory cell.
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Patent Agency Ranking
公开(公告)号：US20230020564A1
公开(公告)日：2023-01-19
申请号：US17404934
申请日：2021-08-17
Applicant: United Microelectronics Corp.
Inventor： Wen-Jen Wang , Chun-Hung Cheng , Chuan-Fu Wang
Abstract: Provided is a resistive random-access memory device, including a dielectric layer located on a substrate, a first electrode which is a column located on the dielectric layer, a second electrode covering a top surface and a sidewall of the first electrode, and a variable resistance layer sandwiched between the top surface of the first electrode and the second electrode and between the sidewall of the first electrode and the second electrode and located between the second electrode and the dielectric layer.
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公开(公告)号：US11538990B2
公开(公告)日：2022-12-27
申请号：US17371376
申请日：2021-07-09
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wen-Jen Wang , Chun-Hung Cheng , Chuan-Fu Wang
Abstract: A method for forming a resistive random access memory structure. The resistive random access memory structure includes a bottom electrode; a variable resistance layer disposed on the bottom electrode; a top electrode disposed on the variable resistance layer; a protection layer surrounding the variable resistance layer, wherein a top surface of the protection layer and a top surface of the top electrode are coplanar; and an upper interconnect structure disposed on the top electrode, wherein the upper interconnect structure is electrically connected to the top electrode and directly contacts a sidewall of the protection layer.
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公开(公告)号：US20220102429A1
公开(公告)日：2022-03-31
申请号：US17084609
申请日：2020-10-29
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wen-Jen Wang , Chun-Hung Cheng , Chuan-Fu Wang
Abstract: A semiconductor device includes a substrate having a memory region and a logic region. A first dielectric layer is disposed on the substrate. A first conductive structure and a second conductive structure are formed in the first dielectric layer and respectively on the memory region and the logic region of the substrate. A memory cell is disposed on the first dielectric layer and directly contacts a top surface of the first conductive structure. A first cap layer is formed on the first dielectric layer and continuously covers a top surface and a sidewall of the memory cell and a top surface of the second conductive structure. A second dielectric layer is formed on the first cap. A third conductive structure is formed in the second dielectric layer and penetrates through the first cap layer to contacts the memory cell.
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公开(公告)号：US20250160226A1
公开(公告)日：2025-05-15
申请号：US18531722
申请日：2023-12-07
Applicant: UNITED MICROELECTRONICS CORP
Inventor： Wen-Jen Wang , Yu-Huan Yeh , Chuan-Fu Wang
Abstract: An RRAM structure includes an RRAM. The RRAM includes a bottom electrode, a variable resistive layer and a top electrode stacked from bottom to top, wherein the bottom electrode is composed of titanium oxide (TiOx), 0
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公开(公告)号：US11632888B2
公开(公告)日：2023-04-18
申请号：US17571519
申请日：2022-01-09
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wen-Jen Wang , Chun-Hung Cheng , Chuan-Fu Wang
Abstract: An RRAM structure includes a substrate. The substrate is divided into a memory cell region and a logic device region. A metal plug is disposed within the memory cell region. An RRAM is disposed on and contacts the metal plug. The RRAM includes a top electrode, a variable resistive layer, and a bottom electrode. The variable resistive layer is disposed between the top electrode and the bottom electrode. The variable resistive layer includes a first bottom surface. The bottom electrode includes a first top surface. The first bottom surface and the first top surface are coplanar. The first bottom surface only overlaps and contacts part of the first top surface.
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