公开(公告)号：US12249649B2

公开(公告)日：2025-03-11

申请号：US17207751

申请日：2021-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Han Wu ,  Hsin-Yu Chen ,  Chun-Hao Lin ,  Shou-Wei Hsieh ,  Chih-Ming Su ,  Yi-Ren Chen ,  Yuan-Ting Chuang

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/417

Abstract: A semiconductor device includes a fin-shaped structure on the substrate, a shallow trench isolation (STI) around the fin-shaped structure, a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure, a second gate structure on the STI, and a third gate structure on the SDB structure. Preferably, a width of the third gate structure is greater than a width of the second gate structure and each of the first gate structure, the second gate structure, and the third gate structure includes a U-shaped high-k dielectric layer, a U-shaped work function metal layer, and a low-resistance metal layer.

公开(公告)号：US10991824B2

公开(公告)日：2021-04-27

申请号：US16252715

申请日：2019-01-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Han Wu ,  Hsin-Yu Chen ,  Chun-Hao Lin ,  Shou-Wei Hsieh ,  Chih-Ming Su ,  Yi-Ren Chen ,  Yuan-Ting Chuang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/417

Abstract: A semiconductor device includes: a fin-shaped structure on the substrate; a shallow trench isolation (STI) around the fin-shaped structure; a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure; a second gate structure on the STI; and a third gate structure on the SDB structure, wherein a width of the third gate structure is greater than a width of the second gate structure.

公开(公告)号：US20170222026A1

公开(公告)日：2017-08-03

申请号：US15014037

申请日：2016-02-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Ren Chen ,  Shou-Wei Hsieh ,  Hsin-Yu Chen ,  Chun-Hao Lin ,  Yuan-Ting Chuang ,  Che-Hung Liu

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/28

CPC classification number: H01L29/66795 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/31111 ,  H01L29/66545 ,  H01L29/7847

Abstract: The present invention provides a method of fabricating a fin field effect transistor (finFET), comprising: firstly, an interfacial layer is formed on a fin structure, next, a high-k dielectric layer is formed on the interfacial layer; afterwards, a stress film is formed on the high-k dielectric layer, an annealing process is then performed to the stress film, and an etching process is performed to remove the stress film.

公开(公告)号：US20170178972A1

公开(公告)日：2017-06-22

申请号：US15447126

申请日：2017-03-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Yu Chang ,  Li-Wei Feng ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Jyh-Shyang Jenq ,  Chien-Ting Lin ,  Yi-Ren Chen ,  Shou-Wei Hsieh ,  Hsin-Yu Chen ,  Chun-Hao Lin

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L21/823821 ,  H01L21/02129 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/66803

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon and a shallow trench isolation (STI) around the fin-shaped structure, in which the fin-shaped structure has a top portion and a bottom portion; forming a first doped layer on the STI and the top portion; and performing a first anneal process.

公开(公告)号：US09627268B2

公开(公告)日：2017-04-18

申请号：US14884746

申请日：2015-10-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Yu Chang ,  Li-Wei Feng ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Jyh-Shyang Jenq ,  Chien-Ting Lin ,  Yi-Ren Chen ,  Shou-Wei Hsieh ,  Hsin-Yu Chen ,  Chun-Hao Lin

IPC: H01L21/8238 ,  H01L21/324

CPC classification number: H01L21/823821 ,  H01L21/02129 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon and a shallow trench isolation (STI) around the fin-shaped structure, in which the fin-shaped structure has a top portion and a bottom portion; forming a first doped layer on the STI and the top portion; and performing a first anneal process.

公开(公告)号：US20210210628A1

公开(公告)日：2021-07-08

申请号：US17207751

申请日：2021-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Han Wu ,  Hsin-Yu Chen ,  Chun-Hao Lin ,  Shou-Wei Hsieh ,  Chih-Ming Su ,  Yi-Ren Chen ,  Yuan-Ting Chuang

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/417

Abstract: A semiconductor device includes a fin-shaped structure on the substrate, a shallow trench isolation (STI) around the fin-shaped structure, a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure, a second gate structure on the STI, and a third gate structure on the SDB structure. Preferably, a width of the third gate structure is greater than a width of the second gate structure and each of the first gate structure, the second gate structure, and the third gate structure includes a U-shaped high-k dielectric layer, a U-shaped work function metal layer, and a low-resistance metal layer.

公开(公告)号：US20170069543A1

公开(公告)日：2017-03-09

申请号：US14884746

申请日：2015-10-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Yu Chang ,  Li-Wei Feng ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Jyh-Shyang Jenq ,  Chien-Ting Lin ,  Yi-Ren Chen ,  Shou-Wei Hsieh ,  Hsin-Yu Chen ,  Chun-Hao Lin

IPC: H01L21/8238 ,  H01L21/324

CPC classification number: H01L21/823821 ,  H01L21/02129 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon and a shallow trench isolation (STI) around the fin-shaped structure, in which the fin-shaped structure has a top portion and a bottom portion; forming a first doped layer on the STI and the top portion; and performing a first anneal process.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有鳍状结构的衬底和围绕鳍状结构的浅沟槽隔离（STI），其中鳍状结构具有顶部和底部; 在STI和顶部上形成第一掺杂层; 并执行第一退火处理。