公开(公告)号：US20250072080A1

公开(公告)日：2025-02-27

申请号：US18372684

申请日：2023-09-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Yih Chen ,  Yi-Wen Chen ,  Chia-Chen Sun ,  Wei-Chung Sun ,  Wan-Ching Lee

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a gate structure on a substrate, forming a first spacer on the gate structure, forming a patterned mask on the gate structure and one side of the gate structure, removing the first spacer on another side of the gate structure, and then forming a source/drain region adjacent to two sides of the gate structure.

公开(公告)号：US20240097038A1

公开(公告)日：2024-03-21

申请号：US17964925

申请日：2022-10-13

Applicant: United Microelectronics Corp.

Inventor： Yi Chuen Eng ,  Tzu-Feng Chang ,  Teng-Chuan Hu ,  Yi-Wen Chen ,  Yu-Hsiang Lin

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0847 ,  H01L29/66795

Abstract: A semiconductor device, including a substrate, a first source/drain region, a second source/drain region, and a gate structure, is provided. The substrate has an extra body portion and a fin protruding from a top surface of the substrate, wherein the fin spans the extra body portion. The first source/drain region and the second source/drain region are in the fin. The gate structure spans the fin, is located above the extra body portion, and is located between the first source/drain region and the second source/drain region.

公开(公告)号：US09825144B2

公开(公告)日：2017-11-21

申请号：US15644850

申请日：2017-07-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Fang Tzou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Hung-Yi Wu ,  Tong-Jyun Huang ,  Chien-Ting Lin ,  Chun-Hsien Lin

IPC: H01L29/76 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/423

CPC classification number: H01L29/4966 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/42364 ,  H01L29/66545

Abstract: A metal gate transistor includes a substrate, a metal gate on the substrate, and a source/drain region in the substrate adjacent to the metal gate. The metal gate includes a high-k dielectric layer, a bottom barrier metal (BBM) layer comprising TiSiN on the high-k dielectric layer, a TiN layer on the BBM layer, a TiAl layer between the BBM layer and the TiN layer, and a low resistance metal layer on the TiN layer.

公开(公告)号：US20170309722A1

公开(公告)日：2017-10-26

申请号：US15644850

申请日：2017-07-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Fang Tzou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Hung-Yi Wu ,  Tong-Jyun Huang ,  Chien-Ting Lin ,  Chun-Hsien Lin

IPC: H01L29/49 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/4966 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/42364 ,  H01L29/66545

Abstract: A metal gate transistor includes a substrate, a metal gate on the substrate, and a source/drain region in the substrate adjacent to the metal gate. The metal gate includes a high-k dielectric layer, a bottom barrier metal (BBM) layer comprising TiSiN on the high-k dielectric layer, a TiN layer on the BBM layer, a TiAl layer between the BBM layer and the TiN layer, and a low resistance metal layer on the TiN layer.

公开(公告)号：US09443952B2

公开(公告)日：2016-09-13

申请号：US14506009

申请日：2014-10-03

Applicant: United Microelectronics Corp.

Inventor： Chun-Tsen Lu ,  Chih-Jung Su ,  Jian-Wei Chen ,  Shui-Yen Lu ,  Yi-Wen Chen ,  Po-Cheng Huang ,  Chen-Ming Huang ,  Shih-Fang Tzou

IPC: H01L21/3205 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/66545 ,  H01L21/0206 ,  H01L21/02065 ,  H01L21/02271 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/4966 ,  H01L29/517

Abstract: A method of forming a semiconductor device is disclosed. A substrate having multiple fins is provided. An insulating layer fills a lower portion of a gap between two adjacent fins. At least one first stacked structure is formed on one fin and at least one second stacked structure is formed on one insulation layer. A first dielectric layer is formed to cover the first and second stacked structures. A portion of the first dielectric layer and portions of the first and second stacked structures are removed. Another portion of the first dielectric layer is removed until a top of the remaining first dielectric layer is lower than tops of the first and second stacked structures. A second dielectric layer is formed to cover the first and second stacked structures. A portion of the second dielectric layer is removed until the tops of the first and second stacked structures are exposed.

Abstract translation: 公开了一种形成半导体器件的方法。 提供具有多个翅片的基板。 绝缘层填充两个相邻翅片之间的间隙的下部。 在一个翅片上形成至少一个第一堆叠结构，并且在一个绝缘层上形成至少一个第二堆叠结构。 形成第一电介质层以覆盖第一和第二堆叠结构。 去除第一电介质层的一部分和第一和第二堆叠结构的部分。 去除第一电介质层的另一部分，直到剩余的第一电介质层的顶部低于第一和第二堆叠结构的顶部。 形成第二电介质层以覆盖第一和第二堆叠结构。 去除第二电介质层的一部分直到第一和第二堆叠结构的顶部露出。

公开(公告)号：US09312356B1

公开(公告)日：2016-04-12

申请号：US14613379

申请日：2015-02-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Yi-Wen Chen

IPC: H01L21/70 ,  H01L29/49 ,  H01L21/02 ,  H01L21/768 ,  H01L21/311 ,  H01L21/28

CPC classification number: H01L29/4966 ,  H01L21/28518 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/41783 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628

Abstract: The semiconductor device includes a gate electrode, a first interlayer dielectric, a first mask layer, a second mask layer and a second interlayer dielectric. The first interlayer dielectric surrounds the periphery of the gate electrode, and the first mask layer is disposed on the gate electrode. The first mask layer and the gate electrode have at least one same metal component. The second mask layer is disposed on the sidewalls of the first mask layer, and the second interlayer dielectric is disposed on the second mask layer and in direct contact with the first interlayer dielectric.

Abstract translation: 半导体器件包括栅电极，第一层间电介质，第一掩模层，第二掩模层和第二层间电介质。 第一层间电介质围绕栅电极的周边，并且第一掩模层设置在栅电极上。 第一掩模层和栅电极具有至少一个相同的金属成分。 第二掩模层设置在第一掩模层的侧壁上，第二层间电介质设置在第二掩模层上并与第一层间电介质直接接触。

公开(公告)号：US09231071B2

公开(公告)日：2016-01-05

申请号：US14187701

申请日：2014-02-24

Applicant: United Microelectronics Corp.

Inventor： Hung-Yi Wu ,  Chien-Ming Lai ,  Yi-Wen Chen

IPC: H01L21/44 ,  H01L21/70 ,  H01L29/49 ,  H01L29/40

CPC classification number: H01L29/4966 ,  H01L29/401 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/78

Abstract: A semiconductor structure and a manufacturing method thereof are disclosed. The semiconductor structure includes an isolation layer, a gate dielectric layer, a first work function metal, a first bottom barrier layer, a second work function metal, and a first top barrier layer. The isolation layer is formed on a substrate and has a first gate trench. The gate dielectric layer is formed in the first gate trench. The first work function metal is formed on the gate dielectric layer in the first gate trench. The first bottom barrier layer is formed on the first work function metal. The second work function metal is formed on the first bottom barrier layer. The first top barrier layer is formed on the second work function metal.

Abstract translation: 公开了一种半导体结构及其制造方法。 半导体结构包括隔离层，栅介质层，第一功函数金属，第一底阻挡层，第二功函数金属和第一顶阻挡层。 隔离层形成在衬底上并具有第一栅极沟槽。 栅介质层形成在第一栅极沟槽中。 第一功函数金属形成在第一栅极沟槽中的栅介质层上。 第一底部阻挡层形成在第一功函数金属上。 第二功能金属形成在第一底部阻挡层上。 第一顶部阻挡层形成在第二功函数金属上。

公开(公告)号：US20240347583A1

公开(公告)日：2024-10-17

申请号：US18195905

申请日：2023-05-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Sheng Yang ,  Yi-Wen Chen ,  Hung-Yi Wu ,  YI CHUEN ENG ,  Yu-Hsiang Lin

IPC: H01L29/06 ,  H01L27/088

CPC classification number: H01L29/0603 ,  H01L27/0886

Abstract: A semiconductor device includes a substrate having a medium-voltage (MV) region and a logic region, a gate structure on the MV region, a first single diffusion break (SDB) structure and a second SDB structure in the substrate directly under the gate structure, and a source/drain region adjacent to two sides of the gate structure. Preferably, top surfaces of the first SDB structure and the second SDB structure are coplanar, bottom surfaces of the first SDB structure and the second SDB structure are coplanar, and the first SDB structure and the second SDB structure are made of same material.

公开(公告)号：US09196546B2

公开(公告)日：2015-11-24

申请号：US14025833

申请日：2013-09-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Fang Tzou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Hung-Yi Wu ,  Tong-Jyun Huang ,  Chien-Ting Lin ,  Chun-Hsien Lin

IPC: H01L29/76 ,  H01L21/8238

CPC classification number: H01L29/4966 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/42364 ,  H01L29/66545

Abstract: A metal gate transistor is disclosed. The metal gate transistor includes a substrate, a metal gate on the substrate, and a source/drain region in the substrate. The metal gate further includes a high-k dielectric layer, a bottom barrier metal (BBM) layer on the high-k dielectric layer, a first work function layer on the BBM layer, a second work function layer between the BBM layer and the first work function layer, and a low resistance metal layer on the first work function layer. Preferably, the first work function layer includes a p-type work function layer and the second work function layer includes a n-type work function layer.

Abstract translation: 公开了一种金属栅极晶体管。 金属栅极晶体管包括衬底，衬底上的金属栅极和衬底中的源极/漏极区域。 金属栅极还包括高k电介质层，高k电介质层上的底部阻挡金属（BBM）层，BBM层上的第一功函数层，BBM层和第一层之间的第二功函数层 功函数层，第一功函数层上的低电阻金属层。 优选地，第一功函数层包括p型功函数层，第二功函数层包括n型功函数层。

公开(公告)号：US09484263B1

公开(公告)日：2016-11-01

申请号：US14926003

申请日：2015-10-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chao-Hung Lin ,  Li-Wei Feng ,  Shih-Hung Tsai ,  Jyh-Shyang Jenq ,  Ching-Ling Lin ,  Yi-Wen Chen ,  Chen-Ming Huang

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/06 ,  H01L21/311

CPC classification number: H01L21/823437 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823468 ,  H01L29/6653 ,  H01L29/66545

Abstract: A method of removing a hard mask on a gate includes forming a first gate structure and a second gate structure. The first gate structure includes a first gate, a first hard mask disposed on the first gate and a first spacer surrounding the first gate and the first hard mask, wherein the second gate structure includes a second gate, a second hard mask disposed on the second gate and a second spacer surrounding the second gate and the second hard mask. Later, the first spacer surrounding the first hard mask and the second spacer surrounding the second hard mask are removed. After that, a dielectric layer is formed to cover the first hard mask and the second hard mask. Finally, the second dielectric layer, the first mask layer and the second mask layer are removed.

Abstract translation: 去除栅极上的硬掩模的方法包括形成第一栅极结构和第二栅极结构。 第一栅极结构包括第一栅极，设置在第一栅极上的第一硬掩模和围绕第一栅极和第一硬掩模的第一隔离物，其中第二栅极结构包括第二栅极，设置在第二栅极上的第二硬掩模 栅极和围绕第二栅极和第二硬掩模的第二隔板。 随后，围绕第一硬掩模的第一间隔物和围绕第二硬掩模的第二间隔物被去除。 之后，形成介电层以覆盖第一硬掩模和第二硬掩模。 最后，去除第二电介质层，第一掩模层和第二掩模层。