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    Fabricating method of transistors without dishing occurred during CMP process
    3.
    发明授权
    Fabricating method of transistors without dishing occurred during CMP process 有权

    公开(公告)号：US11257711B1

    公开(公告)日：2022-02-22

    申请号：US17023391

    申请日：2020-09-17

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Fu-Shou Tsai ,  Yang-Ju Lu ,  Yong-Yi Lin ,  Yu-Lung Shih ,  Ching-Yang Chuang ,  Ji-Min Lin ,  Kun-Ju Li

    IPC: H01L21/768 ,  H01L21/8234 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/02

    Abstract: A fabricating method of transistors includes providing a substrate with numerous transistors thereon. Each of the transistors includes a gate structure. A gap is disposed between gate structures adjacent to each other. Later, a protective layer and a first dielectric layer are formed in sequence to cover the substrate and the transistors and to fill in the gap. Next, numerous buffering particles are formed to contact the first dielectric layer. The buffering particles do not contact each other. Subsequently, a second dielectric layer is formed to cover the buffering particles. After that, a first planarization process is performed to remove part of the first dielectric layer, part of the second dielectric layer and buffering particles by taking the protective layer as a stop layer, wherein a removing rate of the second dielectric layer is greater than a removing rate of the buffering particles during the first planarization process.

    MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    4.
    发明申请
    MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20200185597A1

    公开(公告)日：2020-06-11

    申请号：US16216969

    申请日：2018-12-11

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kun-Ju Li ,  Hsin-Jung Liu ,  I-Ming Tseng ,  Chau-Chung Hou ,  Yu-Lung Shih ,  Fu-Chun Hsiao ,  Hui-Lin Wang ,  Tzu-Hsiang Hung ,  Chih-Yueh Li ,  Ang Chan ,  Jing-Yin Jhang

    IPC: H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  H01L43/12

    Abstract: A memory device includes an insulation layer, a memory cell region and an alignment mark region are defined on the insulation layer, an interconnection structure disposed in the insulation layer, a dielectric layer disposed on the insulation layer and the interconnection structure, the dielectric layer is disposed within the memory cell region and the alignment mark region, a conductive via plug disposed on the interconnection structure within the memory cell region, the conductive via plug has a concave top surface, an alignment mark trench penetrating the dielectric layer within the alignment mark region, a bottom electrode disposed on the conductive via plug within the memory cell region and disposed in the alignment mark trench within the alignment mark region, and a magnetic tunnel junction (MTJ) structure disposed on the bottom electrode within the memory cell region and disposed in the alignment mark trench within the alignment mark region.

    FABRICATING METHOD OF TRANSISTORS WITHOUT DISHING OCCURRED DURING CMP PROCESS
    5.
    发明申请
    FABRICATING METHOD OF TRANSISTORS WITHOUT DISHING OCCURRED DURING CMP PROCESS 有权

    公开(公告)号：US20220084878A1

    公开(公告)日：2022-03-17

    申请号：US17023391

    申请日：2020-09-17

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Fu-Shou Tsai ,  Yang-Ju Lu ,  Yong-Yi Lin ,  Yu-Lung Shih ,  Ching-Yang Chuang ,  Ji-Min Lin ,  Kun-Ju Li

    IPC: H01L21/768 ,  H01L21/8234 ,  H01L21/3105

    Abstract: A fabricating method of transistors includes providing a substrate with numerous transistors thereon. Each of the transistors includes a gate structure. A gap is disposed between gate structures adjacent to each other. Later, a protective layer and a first dielectric layer are formed in sequence to cover the substrate and the transistors and to fill in the gap. Next, numerous buffering particles are formed to contact the first dielectric layer. The buffering particles do not contact each other. Subsequently, a second dielectric layer is formed to cover the buffering particles. After that, a first planarization process is performed to remove part of the first dielectric layer, part of the second dielectric layer and buffering particles by taking the protective layer as a stop layer, wherein a removing rate of the second dielectric layer is greater than a removing rate of the buffering particles during the first planarization process.

    METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE
    9.
    发明申请
    METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE 有权

    公开(公告)号：US20250169079A1

    公开(公告)日：2025-05-22

    申请号：US18404839

    申请日：2024-01-04

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Fu-Shou Tsai ,  Chau-Chung Hou ,  Yong-Yi Lin ,  Yang-Ju Lu ,  Yu-Lung Shih ,  Ren-Peng Huang ,  Ching-Yang Chuang

    IPC: H10B61/00

    Abstract: A method of forming a semiconductor structure. A memory structure is formed on a substrate in the memory array region. A dielectric layer is deposited over the memory array region and peripheral region to cover the memory structure. A reverse etching process is performed to remove part of the dielectric layer from the central area of the memory array region, thereby forming an upwardly protruding wall structure along perimeter of the memory array region. The remaining thickness of the dielectric layer in the central area is equal to the sum of a polishing buffer thickness and a target thickness. A first polishing process is performed to remove the upwardly protruding wall structure from the memory array region. A second polishing process is performed to remove upper portion of the dielectric layer with the polishing buffer thickness from the memory array region.

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