公开(公告)号：US20250169119A1

公开(公告)日：2025-05-22

申请号：US19026289

申请日：2025-01-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Hsuan Tang ,  Chung-Ting Huang ,  Bo-Shiun Chen ,  Chun-Jen Chen ,  Yu-Shu Lin

IPC: H10D30/69 ,  H01L21/02 ,  H10D62/10 ,  H10D64/01

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an epitaxial layer adjacent to the gate structure, and then forming a first cap layer on the epitaxial layer. Preferably, a top surface of the first cap layer includes a curve concave upward and a bottom surface of the first cap layer includes a planar surface higher than a top surface of the substrate.

公开(公告)号：US11990547B2

公开(公告)日：2024-05-21

申请号：US17033897

申请日：2020-09-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yu Chen ,  Bo-Lin Huang ,  Jhong-Yi Huang ,  Keng-Jen Lin ,  Yu-Shu Lin

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/16

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L29/16

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming recesses adjacent to two sides of the gate structure, forming a buffer layer in the recesses, forming a first linear bulk layer on the buffer layer, forming a second linear bulk layer on the first linear bulk layer, forming a bulk layer on the second linear bulk layer, and forming a cap layer on the bulk layer.

公开(公告)号：US11769833B2

公开(公告)日：2023-09-26

申请号：US17956840

申请日：2022-09-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Hsuan Tang ,  Chung-Ting Huang ,  Bo-Shiun Chen ,  Chun-Jen Chen ,  Yu-Shu Lin

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L29/0657 ,  H01L29/6656 ,  H01L29/66553

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an epitaxial layer adjacent to the gate structure, and then forming a first cap layer on the epitaxial layer. Preferably, a top surface of the first cap layer includes a curve concave upward and a bottom surface of the first cap layer includes a planar surface higher than a top surface of the substrate.

公开(公告)号：US11545560B2

公开(公告)日：2023-01-03

申请号：US17160421

申请日：2021-01-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chih Chuang ,  Chia-Jong Liu ,  Kuang-Hsiu Chen ,  Chung-Ting Huang ,  Chi-Hsuan Tang ,  Kai-Hsiang Wang ,  Bing-Yang Jiang ,  Yu-Lin Cheng ,  Chun-Jen Chen ,  Yu-Shu Lin ,  Jhong-Yi Huang ,  Chao-Nan Chen ,  Guan-Ying Wu

IPC: H01L29/66 ,  H01L29/423

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer and a second spacer around the gate structure; forming a recess adjacent to two sides of the second spacer; performing a cleaning process to trim the second spacer for forming a void between the first spacer and the substrate; and forming an epitaxial layer in the recess.

公开(公告)号：US11495686B2

公开(公告)日：2022-11-08

申请号：US17147468

申请日：2021-01-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Hsuan Tang ,  Chung-Ting Huang ,  Bo-Shiun Chen ,  Chun-Jen Chen ,  Yu-Shu Lin

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a gate structure on a substrate, forming a first spacer adjacent to the gate structure, forming a second spacer adjacent to the first spacer, forming an epitaxial layer adjacent to the second spacer, forming a second cap layer on the epitaxial layer, and then forming a first cap layer on the second cap layer. Preferably, a top surface of the first cap layer includes a V-shape and the first cap layer and the second cap layer are made of different materials.

公开(公告)号：US20190214306A1

公开(公告)日：2019-07-11

申请号：US15885834

申请日：2018-02-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Jen Chen ,  Tien-I Wu ,  Yu-Shu Lin

IPC: H01L21/8234 ,  H01L21/324 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure; forming a mask layer on the first fin-shaped structure; and performing a first anneal process so that the first fin-shaped structure and the second fin-shaped structure comprise different radius of curvature.

公开(公告)号：US20150263170A1

公开(公告)日：2015-09-17

申请号：US14723447

申请日：2015-05-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Chang ,  Chun-Yuan Wu ,  Chin-Cheng Chien ,  Tien-Wei Yu ,  Yu-Shu Lin ,  Szu-Hao Lai

IPC: H01L29/78 ,  H01L29/08 ,  H01L21/306 ,  H01L21/324 ,  H01L29/66 ,  H01L29/161

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/3003 ,  H01L21/30604 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636

Abstract: A semiconductor process includes the following steps. Two gates are formed on a substrate. A recess is formed in the substrate beside the gates. A surface modification process is performed on a surface of the recess to modify the shape of the recess and change the contents of the surface.

Abstract translation: 半导体工艺包括以下步骤。 在基板上形成两个栅极。 在栅极旁边的基板中形成凹部。 在凹部的表面上进行表面改性处理，以改变凹部的形状并改变表面的内容物。

公开(公告)号：US08937369B2

公开(公告)日：2015-01-20

申请号：US13633094

申请日：2012-10-01

Applicant: United Microelectronics Corp.

Inventor： Chih-Chien Liu ,  Tzu-Chin Wu ,  Yu-Shu Lin ,  Jei-Ming Chen ,  Wen-Yi Teng

IPC: H01L23/58 ,  H01L21/469

CPC classification number: H01L29/7843 ,  H01L21/02164 ,  H01L21/324 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/6653

Abstract: A transistor includes a semiconductor substrate, at least a gate structure, at least a first tensile stress layer, a second tensile stress layer, a source region, and a drain region. The gate structure is disposed within a first transistor region of the semiconductor substrate. The first tensile stress layer includes a curved portion encompassing the gate structure, at least an extension portion with a curved top surface located on the semiconductor substrate at sides of the gate structure, and a transition portion between the curved portion and the extension portion. The first tensile stress layer has a thickness gradually thinning from the curved portion and the extension portion toward the transition portion. The second tensile stress layer is disposed on the first tensile stress layer. And the source/drain regions are separately located in the semiconductor substrate on two sides of the gate structure.

Abstract translation: 晶体管包括半导体衬底，至少栅极结构，至少第一拉伸应力层，第二拉伸应力层，源极区和漏极区。 栅极结构设置在半导体衬底的第一晶体管区域内。 第一拉伸应力层包括包围栅极结构的弯曲部分，至少一个在栅极结构的侧面处位于半导体衬底上的弯曲顶表面的延伸部分和弯曲部分与延伸部分之间的过渡部分。 第一拉伸应力层具有从弯曲部分和延伸部分朝向过渡部分逐渐变薄的厚度。 第二拉伸应力层设置在第一拉伸应力层上。 并且源极/漏极区域分别位于栅极结构两侧的半导体衬底中。

公开(公告)号：US12300743B2

公开(公告)日：2025-05-13

申请号：US18665600

申请日：2024-05-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chih Chuang ,  Chia-Jong Liu ,  Kuang-Hsiu Chen ,  Chung-Ting Huang ,  Chi-Hsuan Tang ,  Kai-Hsiang Wang ,  Bing-Yang Jiang ,  Yu-Lin Cheng ,  Chun-Jen Chen ,  Yu-Shu Lin ,  Jhong-Yi Huang ,  Chao-Nan Chen ,  Guan-Ying Wu

IPC: H01L29/66 ,  H01L29/423

Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.

公开(公告)号：US20220069127A1

公开(公告)日：2022-03-03

申请号：US17033897

申请日：2020-09-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yu Chen ,  Bo-Lin Huang ,  Jhong-Yi Huang ,  Keng-Jen Lin ,  Yu-Shu Lin

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/16

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming recesses adjacent to two sides of the gate structure, forming a buffer layer in the recesses, forming a first linear bulk layer on the buffer layer, forming a second linear bulk layer on the first linear bulk layer, forming a bulk layer on the second linear bulk layer, and forming a cap layer on the bulk layer.