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    CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF
    1.
    发明申请
    CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF 有权
    电路板及其制造方法

    公开(公告)号：US20170042026A1

    公开(公告)日：2017-02-09

    申请号：US14820572

    申请日：2015-08-07

    Applicant: Unimicron Technology Corp.

    Inventor： Kuan-Hsi Wu ,  Pi-Te Pan ,  Chang-Fu Chen

    IPC: H05K1/11 ,  H05K3/40 ,  H05K3/00 ,  H05K1/02 ,  H05K3/10

    CPC classification number: H05K1/119 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/113 ,  H05K1/116 ,  H05K3/0023 ,  H05K3/0097 ,  H05K3/10 ,  H05K3/303 ,  H05K3/3452 ,  H05K3/4007 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/0367 ,  H05K2201/094 ,  H05K2201/09472 ,  H05K2203/0562 ,  H05K2203/1536 ,  Y02P70/611

    Abstract: A circuit board including a substrate, a photo imageable dielectric layer and a plurality of conductive bumps is provided. The substrate has a first surface and a first circuit layer, wherein the first surface has a chip disposing area and an electrical connection area, and the first circuit layer is embedded in the first surface. The photo imageable dielectric layer is disposed on the electrical connection area and has a plurality of openings, wherein parts of the first circuit layer is exposed by the openings. The conductive bumps are disposed at the openings respectively and connected to the first circuit layer, wherein a side surface of each of the conductive bumps is at least partially covered by the photo imageable dielectric layer. In addition, a manufacturing method of the circuit board is also provided.

    Abstract translation: 提供了包括基板，可光致成像介电层和多个导电凸块的电路板。 基板具有第一表面和第一电路层，其中第一表面具有芯片布置区域和电连接区域，并且第一电路层嵌入在第一表面中。 可光致成像介电层设置在电连接区域上并具有多个开口，其中第一电路层的部分被开口露出。 导电凸块分别设置在开口处并连接到第一电路层，其中每个导电凸块的侧表面至少部分被可光致成像介电层覆盖。 此外，还提供了电路板的制造方法。

    Multi-layer circuit structure and manufacturing method thereof
    2.
    发明授权
    Multi-layer circuit structure and manufacturing method thereof 有权

    公开(公告)号：US10383226B2

    公开(公告)日：2019-08-13

    申请号：US15836923

    申请日：2017-12-11

    Applicant: Unimicron Technology Corp.

    Inventor： Chang-Fu Chen ,  Chun-Hao Chen

    IPC: H05K3/46 ,  H05K1/11 ,  H05K3/42 ,  H05K3/00

    Abstract: A multi-layer circuit structure including a core layer, a first circuit structure, a second circuit structure, and a build-up circuit structure is provided. The first circuit structure and the second circuit structure are respectively disposed on two opposite surfaces of the core layer. The build-up circuit structure includes a first dielectric layer disposed on the first circuit structure, first conductive blind holes, a second dielectric layer disposed on the first dielectric layer, second conductive blind holes, and a patterned circuit layer disposed on the second dielectric layer. The first conductive blind holes penetrate through the first dielectric layer and electrically contact the first circuit structure. The second conductive blind holes penetrate through the second dielectric layer and electrically contact the first conductive blind holes respectively. The patterned circuit layer electrically contacts the second conductive blind holes. A manufacturing method of the multi-layer circuit structure is also provided.

    Package structure
    6.
    发明授权
    Package structure 有权

    公开(公告)号：US11476199B2

    公开(公告)日：2022-10-18

    申请号：US17200892

    申请日：2021-03-14

    Applicant: Unimicron Technology Corp.

    Inventor： Yi Lin ,  Chun-Ming Chiu ,  Hung-Chih Lee ,  Chang-Fu Chen

    IPC: H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H01L21/48

    Abstract: A package structure includes a first substrate, a second substrate, a plurality of dies, a plurality of first conductive elements, and a plurality of second conductive elements. The first substrate has a recessed region. The second substrate is disposed in the recessed region and protrudes from the first substrate. The dies are disposed on the first substrate and the second substrate, such that the second substrate is disposed between the first substrate and the dies. The first conductive elements are disposed between the dies and the first substrate. The dies are electrically connected with the first substrate through the first conductive elements. The second conductive elements are disposed between the dies and the second substrate. The dies are electrically connected with the second substrate through the second conductive elements.

    Circuit carrier structure and manufacturing method thereof
    7.
    发明授权
    Circuit carrier structure and manufacturing method thereof 有权

    公开(公告)号：US11153963B2

    公开(公告)日：2021-10-19

    申请号：US16845069

    申请日：2020-04-10

    Applicant: Unimicron Technology Corp.

    Inventor： Chang-Fu Chen ,  Ho-Shing Lee ,  Chien-Chen Lin

    IPC: H05K1/02 ,  H05K3/00 ,  H05K1/11 ,  H05K3/06 ,  H05K3/46

    Abstract: A circuit carrier structure includes an inner circuit structure, at least one first circuit layer, and at least one heat dissipating structure. The inner circuit structure has a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface of the inner circuit structure. The heat dissipating structure is disposed in the first circuit layer. The heat dissipating structure includes a first heat dissipating pattern, a second heat dissipating pattern and an interlayer metal layer. The first heat dissipating pattern is embedded in the corresponding first circuit layer. The second heat dissipating pattern is disposed on the first heat dissipating pattern. The interlayer metal layer is disposed between the first heat dissipating pattern and the second heat dissipating pattern. A manufacturing method of the circuit carrier structure is also provided.

    Package structure
    8.
    发明授权
    Package structure 有权

    公开(公告)号：US10978401B2

    公开(公告)日：2021-04-13

    申请号：US16000912

    申请日：2018-06-06

    Applicant: Unimicron Technology Corp.

    Inventor： Yi Lin ,  Chun-Ming Chiu ,  Hung-Chih Lee ,  Chang-Fu Chen

    IPC: H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H01L21/48

    Abstract: A package structure includes a first substrate, a second substrate, a plurality of dies, a plurality of first conductive elements, and a plurality of second conductive elements. The first substrate has a recessed region. The second substrate is disposed in the recessed region and protrudes from the first substrate. The dies are disposed on the first substrate and the second substrate, such that the second substrate is disposed between the first substrate and the dies. The first conductive elements are disposed between the dies and the first substrate. The dies are electrically connected with the first substrate through the first conductive elements. The second conductive elements are disposed between the dies and the second substrate. The dies are electrically connected with the second substrate through the second conductive elements.

    CIRCUIT CARRIER STRUCTURE AND MANUFACTURING METHOD THEREOF
    9.
    发明申请
    CIRCUIT CARRIER STRUCTURE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20210289614A1

    公开(公告)日：2021-09-16

    申请号：US16845069

    申请日：2020-04-10

    Applicant: Unimicron Technology Corp.

    Inventor： Chang-Fu Chen ,  Ho-Shing Lee ,  Chien-Chen Lin

    IPC: H05K1/02 ,  H05K3/00 ,  H05K3/46 ,  H05K3/06 ,  H05K1/11

    Abstract: A circuit carrier structure includes an inner circuit structure, at least one first circuit layer, and at least one heat dissipating structure. The inner circuit structure has a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface of the inner circuit structure. The heat dissipating structure is disposed in the first circuit layer. The heat dissipating structure includes a first heat dissipating pattern, a second heat dissipating pattern and an interlayer metal layer. The first heat dissipating pattern is embedded in the corresponding first circuit layer. The second heat dissipating pattern is disposed on the first heat dissipating pattern. The interlayer metal layer is disposed between the first heat dissipating pattern and the second heat dissipating pattern. A manufacturing method of the circuit carrier structure is also provided.

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