公开(公告)号：US12108530B2

公开(公告)日：2024-10-01

申请号：US17899583

申请日：2022-08-30

Applicant: Unimicron Technology Corp.

Inventor： Kuang-Ching Fan ,  Chih-Peng Hsieh ,  Cheng-Hsiung Wang

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/46

CPC classification number: H05K1/112 ,  H05K3/4644 ,  H05K1/0284 ,  H05K1/0298 ,  H05K1/113 ,  H05K2201/098

Abstract: A circuit board structure includes a circuit substrate, a first circuit layer, and a second circuit layer. The circuit substrate has a surface and includes at least one conductive structure and at least one patterned circuit layer. The conductive structure is electrically connected to the patterned circuit layer, and an upper surface of the conductive structure is aligned with the surface. The first circuit layer is directly disposed on the surface of the circuit substrate and electrically connected to the conductive structure. A line width of the first circuit layer is less than or equal to 1/4 of a line width of the patterned circuit layer. The second circuit layer is directly disposed on the first circuit layer and electrically connected to the first circuit layer.

公开(公告)号：US20230225050A1

公开(公告)日：2023-07-13

申请号：US17899583

申请日：2022-08-30

Applicant: Unimicron Technology Corp.

Inventor： Kuang-Ching Fan ,  Chih-Peng Hsieh ,  Cheng-Hsiung Wang

IPC: H05K1/11 ,  H05K3/46

CPC classification number: H05K1/112 ,  H05K3/4644

Abstract: A circuit board structure includes a circuit substrate, a first circuit layer, and a second circuit layer. The circuit substrate has a surface and includes at least one conductive structure and at least one patterned circuit layer. The conductive structure is electrically connected to the patterned circuit layer, and an upper surface of the conductive structure is aligned with the surface. The first circuit layer is directly disposed on the surface of the circuit substrate and electrically connected to the conductive structure. A line width of the first circuit layer is less than or equal to ¼ of a line width of the patterned circuit layer. The second circuit layer is directly disposed on the first circuit layer and electrically connected to the first circuit layer.