公开(公告)号：US20230137841A1

公开(公告)日：2023-05-04

申请号：US18089465

申请日：2022-12-27

Applicant: Unimicron Technology Corp.

Inventor： John Hon-Shing Lau ,  Ra-Min Tain ,  Cheng-Ta Ko ,  Tzyy-Jang Tseng ,  Chun-Hsien Chien

IPC: H05K3/46 ,  H05K1/11 ,  H05K3/40 ,  H05K3/00

Abstract: A circuit carrier includes a substrate, a first build-up circuit structure, a second build-up circuit structure, a fine redistribution structure and at least one conductive through hole. The substrate has a top surface and a bottom surface opposite to each other. The first build-up circuit structure is disposed on the top surface of the substrate and electrically connected to the substrate. The second build-up circuit structure is disposed on the bottom surface of the substrate and electrically connected to the substrate. The fine redistribution structure is directly attached on the first build-up circuit structure, wherein a line width and a line spacing of the fine redistribution structure are smaller than those of the first build-up circuit structure. The conductive through hole penetrates the fine redistribution structure and a portion of the first build-up circuit structure and is electrically connected to the fine redistribution structure and the first build-up circuit structure.

公开(公告)号：US11532543B2

公开(公告)日：2022-12-20

申请号：US17402635

申请日：2021-08-16

Applicant: Unimicron Technology Corp.

Inventor： Wei-Ti Lin ,  Chun-Hsien Chien ,  Yu-Hua Chen

IPC: H05K1/03 ,  H01L23/498 ,  H01L21/48 ,  H05K1/18

Abstract: A package carrier includes a substrate, at least one interposer disposed in at least one opening of the substrate, a conductive structure layer, a first build-up structure, and a second build-up structure. The interposer includes a glass substrate, at least one conductive via, at least one first pad, and at least one second pad. The conductive via passes through the glass substrate, and the first and the second pads are disposed respectively on an upper surface and a lower surface of the glass substrate opposite to each other and are connected to opposite ends of the conductive via. The conductive structure layer is disposed on the substrate and is structurally and electrically connected to the first and the second pads. The first and the second build-up structures are disposed respectively on the first and the second surfaces of the substrate and are electrically connected to the conductive structure layer.

公开(公告)号：US11201123B2

公开(公告)日：2021-12-14

申请号：US16673967

申请日：2019-11-05

Applicant: Unimicron Technology Corp.

Inventor： Chun-Hsien Chien ,  Po-Chen Lin ,  Wen-Liang Yeh ,  Chien-Chou Chen

IPC: H01L23/15 ,  H01L23/00 ,  H01L23/498 ,  H01L23/66 ,  H01L21/48 ,  H01Q1/24

Abstract: A substrate structure includes a glass substrate, a first circuit layer, a second circuit layer, and at least one conductive region. The glass substrate has a first surface and a second surface opposing the first surface. The first circuit layer is disposed on the first surface. The second circuit layer is disposed on the second surface. The conductive region includes a plurality of conductive micro vias. The conductive micro vias penetrate through the glass substrate. The conductive micro vias are electrically connected to the first circuit layer and the second circuit layer, and the conductive micro vias have a via size of 2 μm to 10 μm.

公开(公告)号：US20200266181A1

公开(公告)日：2020-08-20

申请号：US16869595

申请日：2020-05-08

Applicant: Unimicron Technology Corp.

Inventor： Wei-Ti Lin ,  Chun-Hsien Chien ,  Fu-Yang Chen

IPC: H01L25/16 ,  H01L23/00 ,  H01L25/075 ,  H01L33/62

Abstract: A manufacturing method of the light-emitting diode package structure is provided. A carrier is formed. The carrier comprises a first build-up circuit. At least one self-assembled material layer is formed on the first build-up circuit. A first solder mask layer is formed on the first build-up circuit. The first solder mask layer has at least one opening to expose a portion of the at least one self-assembled material layer. At least one light-emitting diode is disposed on the first build-up circuit. The at least one light-emitting diode has a self-assembled pattern, and the at least one light-emitting diode is self-assembled into the at least one opening of the first solder mask layer through a force between the self-assembled pattern and the at least one self-assembled material layer.

公开(公告)号：US20200013744A1

公开(公告)日：2020-01-09

申请号：US16181374

申请日：2018-11-06

Applicant: Unimicron Technology Corp.

Inventor： Yu-Chung Hsieh ,  Chun-Hsien Chien ,  Yu-Hua Chen

IPC: H01L23/00 ,  H01L21/027 ,  H01L21/768

Abstract: A circuit board element including an insulating layer, a circuit layer, a protective layer, a plurality of solder balls, and a dielectric layer is provided. The circuit layer is disposed on the insulating layer. The protective layer is disposed on the circuit layer and has a plurality of openings exposing the circuit layer. The plurality of solder balls are disposed on the protective layer and embedded in the corresponding openings. The dielectric layer is disposed between the solder balls and the protective layer. A manufacturing method of a circuit board element is also provided.

公开(公告)号：US11678441B2

公开(公告)日：2023-06-13

申请号：US16950910

申请日：2020-11-18

Applicant: Unimicron Technology Corp.

Inventor： Wei-Ti Lin ,  Chun-Hsien Chien ,  Chien-Chou Chen ,  Fu-Yang Chen ,  Ra-Min Tain

IPC: H05K3/46 ,  H05K3/40 ,  H05K3/42 ,  H05K3/28 ,  H05K3/30 ,  H05K1/11 ,  H05K1/18 ,  H05K3/00

CPC classification number: H05K3/4644 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181 ,  H05K3/007 ,  H05K3/0097 ,  H05K3/28 ,  H05K3/303 ,  H05K3/4007 ,  H05K3/421 ,  H05K3/429 ,  H05K2201/09136 ,  H05K2201/09509 ,  H05K2201/09827 ,  H05K2201/10234 ,  H05K2201/10522

Abstract: A circuit carrier board structure includes a first substrate, a second substrate, an adhesive layer, and a plurality of contact pads. The first substrate includes a first surface and a second surface, and also includes a plurality of first build-up layers sequentially stacked. The first build-up layers include a first dielectric layer and a first circuit layer. The second substrate includes a third surface and a fourth surface, and also includes a plurality of second build-up layers sequentially stacked. The second build-up layers include a second dielectric layer and a second circuit layer. The second surface is combined to the third surface. The connection pads are on the first surface and electrically connected to the first circuit layer. The first substrate is electrically connected to the second substrate. A manufacturing method of the circuit carrier board structure is also provided.

公开(公告)号：US11579178B1

公开(公告)日：2023-02-14

申请号：US17647012

申请日：2022-01-04

Applicant: Unimicron Technology Corp.

Inventor： Hsin-Hung Lee ,  Chun-Hsien Chien ,  Yu-Chung Hsieh ,  Yi-Hsiu Fang ,  Tzyy-Jang Tseng

IPC: G01R29/08

Abstract: An inspection apparatus used for inspecting a bare circuit board is provided, where the bare circuit board includes an antenna. The inspection apparatus includes a holding stage, a probing device, and a measurement device. The holding stage can hold the bare circuit board. The measurement device is electrically connected to the probing device and electrically connected to the antenna via the probing device. The measurement device can input a first testing signal to the antenna. The antenna can input a second testing signal to the measurement device after receiving the first testing signal. The measurement device can measure the antenna according to the second testing signal, where the first testing signal and the second testing signal both pass through no active component.

公开(公告)号：US20220022316A1

公开(公告)日：2022-01-20

申请号：US16996911

申请日：2020-08-19

Applicant: Unimicron Technology Corp.

Inventor： Po-Wei Chen ,  Wei-Ti Lin ,  Chun-Hsien Chien

IPC: H05K1/11 ,  H05K3/10 ,  H05K3/46 ,  H05K3/18 ,  H01L23/498

Abstract: A package carrier includes a build-up circuit structure, a first insulation protective layer, a plurality of connection pads, and a plurality of metal balls. The build-up circuit structure has an upper surface. The first insulation protective layer is disposed on the upper surface of the build-up circuit structure and has a plurality of first openings. The connection pads are respectively disposed in the first openings of the first insulation protective layer and are structurally and electrically connected to the build-up circuit structure. Each of the connection pads has an arc-shaped groove. The metal balls are respectively disposed in the arc-shaped groove of the connection pads. The metal balls and the corresponding connection pads define a plurality of bump structures, and a plurality of top surfaces of the bump structures are on a same plane.

公开(公告)号：US11037869B2

公开(公告)日：2021-06-15

申请号：US16690143

申请日：2019-11-21

Applicant: Unimicron Technology Corp.

Inventor： Fu-Yang Chen ,  Chun-Hsien Chien ,  Cheng-Hui Wu ,  Wei-Ti Lin

IPC: H01L21/48 ,  H01L23/498

Abstract: A method of preparing a package structure is provided, which includes providing a carrier plate including a supporting layer, a first release layer, and a first metal layer; forming a first dielectric layer over the first metal layer, the first dielectric layer having a plurality of holes, each of the holes having an end portion substantially coplanar with each other at a same plane; forming a plurality of conductive protrusions filling the holes, each of the conductive protrusions having a first end and a second end opposite thereto; forming a circuit layer structure including at least one circuit layer and at least one second dielectric layer, the circuit layer being connected to the second end, the second dielectric layer being disposed over the circuit layer; removing the carrier plate; and removing a portion of the first dielectric layer to expose the conductive protrusions. A package structure is also provided.

公开(公告)号：US20200163215A1

公开(公告)日：2020-05-21

申请号：US16221587

申请日：2018-12-17

Applicant: Unimicron Technology Corp.

Inventor： Wen-Liang Yeh ,  Chun-Hsien Chien ,  Chien-Chou Chen ,  Cheng-Hui Wu

IPC: H05K1/11 ,  H05K1/03 ,  H05K3/28 ,  H05K3/00

Abstract: A carrier structure including a glass substrate, a buffer layer, and an inner circuit layer is provided. The glass substrate has a first surface, a second surface opposite to the first surface, and at least one through hole penetrating through the glass substrate. The buffer layer is disposed on the first surface and the second surface of the glass substrate. The inner circuit layer is disposed on the buffer layer and in the through hole of the glass substrate. The inner circuit layer exposes a part of the buffer layer.