公开(公告)号：US20200163215A1

公开(公告)日：2020-05-21

申请号：US16221587

申请日：2018-12-17

Applicant: Unimicron Technology Corp.

Inventor： Wen-Liang Yeh ,  Chun-Hsien Chien ,  Chien-Chou Chen ,  Cheng-Hui Wu

IPC: H05K1/11 ,  H05K1/03 ,  H05K3/28 ,  H05K3/00

Abstract: A carrier structure including a glass substrate, a buffer layer, and an inner circuit layer is provided. The glass substrate has a first surface, a second surface opposite to the first surface, and at least one through hole penetrating through the glass substrate. The buffer layer is disposed on the first surface and the second surface of the glass substrate. The inner circuit layer is disposed on the buffer layer and in the through hole of the glass substrate. The inner circuit layer exposes a part of the buffer layer.

公开(公告)号：US11201123B2

公开(公告)日：2021-12-14

申请号：US16673967

申请日：2019-11-05

Applicant: Unimicron Technology Corp.

Inventor： Chun-Hsien Chien ,  Po-Chen Lin ,  Wen-Liang Yeh ,  Chien-Chou Chen

IPC: H01L23/15 ,  H01L23/00 ,  H01L23/498 ,  H01L23/66 ,  H01L21/48 ,  H01Q1/24

Abstract: A substrate structure includes a glass substrate, a first circuit layer, a second circuit layer, and at least one conductive region. The glass substrate has a first surface and a second surface opposing the first surface. The first circuit layer is disposed on the first surface. The second circuit layer is disposed on the second surface. The conductive region includes a plurality of conductive micro vias. The conductive micro vias penetrate through the glass substrate. The conductive micro vias are electrically connected to the first circuit layer and the second circuit layer, and the conductive micro vias have a via size of 2 μm to 10 μm.

公开(公告)号：US20210219435A1

公开(公告)日：2021-07-15

申请号：US17219898

申请日：2021-04-01

Applicant: Unimicron Technology Corp.

Inventor： Chun-Hsien Chien ,  Wen-Liang Yeh ,  Wei-Ti Lin

IPC: H05K3/46 ,  H05K1/11 ,  H05K3/40 ,  H05K3/00

Abstract: A circuit carrier board includes a first build-up layer structure, a substrate, an adhesive layer, and a conductive structure. The first build-up layer includes a plurality of first dielectric layers and a plurality of first circuit layers original stacked. The substrate includes a base and a second build-up layer structure disposed on the base. The second build-up layer structure includes a plurality of second dielectric layers and a plurality of second circuit layer original stacked. A top most layer of the second circuit layers is exposed outside of the second dielectric layers. The conductive structure penetrates through the first dielectric layers, the first circuit layers and the adhesive layer, and contacts with the top most layer of the second circuit layers. The conductive structure electrical connects the first circuit layers to the second circuit layers. A manufacturing method of the circuit carrier board is also provided.

公开(公告)号：US10999939B2

公开(公告)日：2021-05-04

申请号：US16535102

申请日：2019-08-08

Applicant: Unimicron Technology Corp.

Inventor： Chun-Hsien Chien ,  Wen-Liang Yeh ,  Wei-Ti Lin

IPC: H05K7/10 ,  H05K7/12 ,  H05K3/46 ,  H05K1/11 ,  H05K3/40 ,  H05K3/00

Abstract: A circuit carrier board includes a first build-up layer structure, a substrate, an adhesive layer, and a conductive structure. The first build-up layer includes a plurality of first dielectric layers and a plurality of first circuit layers original stacked. The substrate includes a base and a second build-up layer structure disposed on the base. The second build-up layer structure includes a plurality of second dielectric layers and a plurality of second circuit layer original stacked. A top most layer of the second circuit layers is exposed outside of the second dielectric layers. The conductive structure penetrates through the first dielectric layers, the first circuit layers and the adhesive layer, and contacts with the top most layer of the second circuit layers. The conductive structure electrical connects the first circuit layers to the second circuit layers. A manufacturing method of the circuit carrier board is also provided.

公开(公告)号：US10461146B1

公开(公告)日：2019-10-29

申请号：US16151351

申请日：2018-10-04

Applicant: Unimicron Technology Corp.

Inventor： Wen-Liang Yeh ,  Chun-Hsien Chien ,  Chien-Chou Chen ,  Cheng-Hui Wu

IPC: H01L21/02 ,  H01L49/02 ,  H01L23/00 ,  H01L23/522

Abstract: A package structure includes a substrate, a metal-insulator-metal capacitor, a circuit redistribution structure, and a chip. The metal-insulator-metal capacitor is disposed over the substrate and includes a first electrode, a second electrode, and an insulating layer. The circuit redistribution structure is disposed over the metal-insulator-metal capacitor and includes a first circuit redistribution layer and a second circuit redistribution layer. The first circuit redistribution layer includes a first wire electrically connected to the first electrode and a second wire electrically connected to the second electrode. The second circuit redistribution layer is disposed on the first circuit redistribution layer and includes a third wire electrically connected to the first wire and a fourth wire electrically connected to the second wire. The chip is disposed over the circuit redistribution structure and electrically connected to the third wire and the fourth wire.

公开(公告)号：US20220287182A1

公开(公告)日：2022-09-08

申请号：US17826178

申请日：2022-05-27

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Yu-Hua Chen ,  Chun-Hsien Chien ,  Wen-Liang Yeh ,  Ra-Min Tain

IPC: H05K1/18 ,  H05K1/02 ,  H05K3/46

Abstract: An embedded component structure includes a board, an electronic component, and a dielectric material layer. The board has a through cavity. The board includes an insulating core layer and a conductive member. The insulating core layer has a first surface and a second surface opposite thereto. The through cavity penetrates the insulating core layer. The conductive member extends from a portion of the first surface along a portion of the side wall of the through cavity to a portion of the second surface. The electronic component includes an electrode. The electronic component is disposed in the through cavity. The dielectric material layer is at least filled in the through cavity. The connection circuit layer covers and contacts the conductive member and the electrode. A manufacturing method of an embedded component structure is also provided.

公开(公告)号：US11348869B2

公开(公告)日：2022-05-31

申请号：US17100932

申请日：2020-11-22

Applicant: Unimicron Technology Corp.

Inventor： Chien-Chou Chen ,  Chun-Hsien Chien ,  Wen-Liang Yeh ,  Wei-Ti Lin

IPC: H01L23/04 ,  H01L23/522 ,  H01L23/00 ,  H01L21/50

Abstract: A chip packaging structure includes a circuit redistribution structure, a chip, a sealing layer, and an antenna pattern. The circuit redistribution structure includes a first and a second circuit layer, and a conductive pad. The second circuit layer is disposed on and electrically connected to the first circuit layer. The conductive pad is electrically connected to the second circuit layer. The chip is disposed on the circuit redistribution structure and electrically connected to the second circuit layer. The sealing layer having an opening and a groove covers the chip and the circuit redistribution structure. The opening exposes the conductive pad. A portion of the groove communicates with the opening. The antenna pattern includes a first and a second portion. The first portion covers sidewalls of the opening and is electrically connected to the conductive pad. The second portion is filled in the groove and electrically connected to the first portion.

公开(公告)号：US10660202B1

公开(公告)日：2020-05-19

申请号：US16221587

申请日：2018-12-17

Applicant: Unimicron Technology Corp.

Inventor： Wen-Liang Yeh ,  Chun-Hsien Chien ,  Chien-Chou Chen ,  Cheng-Hui Wu

IPC: H05K1/00 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K1/18 ,  H05K3/00 ,  H05K3/02 ,  H05K3/10 ,  H05K3/30 ,  H05K3/46 ,  H05K3/28 ,  H05K3/34

Abstract: A carrier structure including a glass substrate, a buffer layer, and an inner circuit layer is provided. The glass substrate has a first surface, a second surface opposite to the first surface, and at least one through hole penetrating through the glass substrate. The buffer layer is disposed on the first surface and the second surface of the glass substrate. The inner circuit layer is disposed on the buffer layer and in the through hole of the glass substrate. The inner circuit layer exposes a part of the buffer layer.