公开(公告)号：US20190019731A1

公开(公告)日：2019-01-17

申请号：US15647031

申请日：2017-07-11

Applicant: United Microelectronics Corp.

Inventor： Ching-Ling Lin ,  Wen-An Liang ,  Chen-Ming Huang

IPC: H01L21/8234 ,  H01L21/033

Abstract: A method for fabricating a semiconductor structure includes forming a plurality of mandrels over a substrate, wherein the substrate comprises a semiconductor substrate as a base. Then, a first dielectric layer is formed to cover on a predetermined mandrel of the mandrels. A second dielectric layer is formed over the substrate to cover the mandrels. The mandrels are removed, wherein a remaining portion of the first dielectric layer and the second dielectric layer at a sidewall of the mandrels remains on the substrate. An anisotropic etching process is performed over the substrate until a top portion of the semiconductor substrate is etched to form a plurality of fins corresponding to the remaining portion of the first dielectric layer and the second dielectric layer.

公开(公告)号：US10032675B2

公开(公告)日：2018-07-24

申请号：US15473614

申请日：2017-03-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Ming Tseng ,  Wen-An Liang ,  Chen-Ming Huang

IPC: H01L29/76 ,  H01L29/94 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L23/535

Abstract: The present invention further provides a method for forming a semiconductor device, comprising: first, a substrate having a fin structure disposed thereon is provided, wherein the fin structure has a trench, next, a first liner in the trench is formed, a first insulating layer is formed on the first liner, afterwards, a shallow trench isolation is formed in the substrate and surrounding the fin structure, wherein a bottom surface of the shallow trench isolation is higher than a bottom surface of the first insulating layer, and a top surface of the shallow trench isolation is lower than a top surface of the first insulating layer, and a dummy gate structure is formed on the first insulating layer and disposed above the trench, wherein a bottom surface of the dummy gate structure and a top surface of the fin structure are on a same level.

公开(公告)号：US09824931B2

公开(公告)日：2017-11-21

申请号：US14981929

申请日：2015-12-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Ming Tseng ,  Wen-An Liang ,  Chen-Ming Huang

IPC: H01L29/06 ,  H01L29/78 ,  H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/76 ,  H01L21/28 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L29/49

CPC classification number: H01L21/823481 ,  H01L21/0228 ,  H01L21/31105 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823456 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a first shallow trench isolation (STI) around the fin-shaped structure; dividing the fin-shaped structure into a first portion and a second portion; and forming a second STI between the first portion and the second portion.

公开(公告)号：US09748144B1

公开(公告)日：2017-08-29

申请号：US15138228

申请日：2016-04-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Yi-Wen Chen ,  Chen-Ming Huang ,  Ren-Peng Huang ,  Ching-Fu Lin

IPC: H01L21/00 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/3213 ,  H01L29/423 ,  H01L21/321 ,  H01L21/033 ,  H01L29/51 ,  H01L21/28 ,  H01L27/11

CPC classification number: H01L21/823456 ,  H01L21/0332 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/31055 ,  H01L21/32115 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/1104 ,  H01L27/1116 ,  H01L28/00 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: First and second semiconductor structures, a CESL, and an ILD layer are formed on a substrate. The first semiconductor structure includes first dummy gate, first nitride mask, and first oxide mask. The second semiconductor structure includes second dummy gate, second nitride mask, and second oxide mask. A first planarization is performed to remove a portion of the ILD layer, exposing CESL. A portion of the CESL, a portion of the ILD layer, the first and the second oxide masks are removed. A hard mask layer is formed on the first and the second nitride masks, and in a recess of the ILD layer. A second planarization is performed to remove a portion of the hard mask layer, the first and the second nitride masks, exposing first and second dummy gates. A remaining portion of the hard mask layer covers the ILD layer.

公开(公告)号：US20170092643A1

公开(公告)日：2017-03-30

申请号：US14864908

申请日：2015-09-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Ming Tseng ,  Wen-An Liang ,  Chen-Ming Huang

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/3105

CPC classification number: H01L27/0886 ,  H01L21/3081 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0653

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, a plurality of fin shaped structures, a first trench and at least one bump. The substrate has a base. The fin shaped structures protrude from the base of the substrate. The first trench recesses from the base of the substrate and has a depth being smaller than a width of each of the fin shaped structures. The at least one bump is disposed on a surface of the first trench.

公开(公告)号：US20160276429A1

公开(公告)日：2016-09-22

申请号：US14684445

申请日：2015-04-13

Applicant: United Microelectronics Corp.

Inventor： I-Ming Tseng ,  Wen-An Liang ,  Rai-Min Huang ,  Chen-Ming Huang ,  Tong-Jyun Huang ,  Kuan-Hsien Li

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/762 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/66545 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/7851

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a fin shaped structure, a spacer layer and a dummy gate structure. The fin shaped structure is disposed on a substrate, wherein the fin shaped structure has a trench. The spacer layer is disposed on sidewalls of the trench. The dummy gate structure is disposed across the trench and includes a portion thereof disposed in the trench.

Abstract translation: 半导体器件及其形成方法，半导体器件包括鳍状结构，间隔层和虚拟栅极结构。 鳍状结构设置在基板上，其中鳍状结构具有沟槽。 间隔层设置在沟槽的侧壁上。 伪栅极结构跨越沟槽设置并且包括其设置在沟槽中的部分。

公开(公告)号：US20150255563A1

公开(公告)日：2015-09-10

申请号：US14195967

申请日：2014-03-04

Applicant: United Microelectronics Corp.

Inventor： Yen-Liang Wu ,  Chung-Fu Chang ,  Yu-Hsiang Hung ,  Man-Ling Lu ,  Cho-Han Fan ,  Ssu-I Fu ,  Chen-Ming Huang

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/28123 ,  H01L21/3086 ,  H01L21/32139 ,  H01L29/6653 ,  H01L29/66795

Abstract: A method for manufacturing a semiconductor device is provided, comprising steps of providing a substrate with an underlying layer formed thereon; forming a gate layer overlying the underlying layer; and forming a multi-layer hard mask layer on the gate layer, and the multi-layer hard mask layer comprising a plurality of material layers and a top hard mask formed on the material layers, wherein the gate layer and the top hard mask contain the same element, such as silicon.

Abstract translation: 提供了一种用于制造半导体器件的方法，包括以下步骤：提供其上形成有底层的衬底; 形成覆盖下层的栅极层; 以及在所述栅极层上形成多层硬掩模层，所述多层硬掩模层包括多个材料层和形成在所述材料层上的顶部硬掩模，其中所述栅极层和所述顶部硬掩模含有 相同的元素，如硅。

公开(公告)号：US10679903B2

公开(公告)日：2020-06-09

申请号：US15859775

申请日：2018-01-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Wen-An Liang ,  Chen-Ming Huang

IPC: H01L21/8234 ,  H01L21/764 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a first gate structure and a second gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; transforming the first gate structure and the second gate structure into a first metal gate and a second metal gate; forming a hard mask on the first metal gate and the second metal gate; removing part of the hard mask, the second metal gate, and part of the fin-shaped structure to form a trench; and forming a dielectric layer into the trench to form a single diffusion break (SDB) structure.

公开(公告)号：US20190172753A1

公开(公告)日：2019-06-06

申请号：US15859775

申请日：2018-01-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Wen-An Liang ,  Chen-Ming Huang

IPC: H01L21/8234 ,  H01L21/764 ,  H01L27/088 ,  H01L29/06

Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a first gate structure and a second gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; transforming the first gate structure and the second gate structure into a first metal gate and a second metal gate; forming a hard mask on the first metal gate and the second metal gate; removing part of the hard mask, the second metal gate, and part of the fin-shaped structure to form a trench; and forming a dielectric layer into the trench to form a single diffusion break (SDB) structure.

公开(公告)号：US10008581B2

公开(公告)日：2018-06-26

申请号：US14840041

申请日：2015-08-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Tsen Lu ,  Chien-Ming Lai ,  Lu-Sheng Chou ,  Ya-Huei Tsai ,  Ching-Hsiang Chiu ,  Yu-Tung Hsiao ,  Chen-Ming Huang ,  Kun-Ju Li ,  Yu-Ping Wang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  C22C32/00 ,  H01L29/51 ,  H01L21/28 ,  B32B1/00

CPC classification number: H01L29/66545 ,  B32B1/00 ,  B32B18/00 ,  C22C32/0068 ,  H01L21/28088 ,  H01L29/4238 ,  H01L29/4966 ,  H01L29/511

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate and a gate structure on the substrate. The gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, in which the top portion being a nitrogen rich portion, and the middle portion and the bottom portion being titanium rich portions.