公开(公告)号：US20190043877A1

公开(公告)日：2019-02-07

申请号：US15665437

申请日：2017-08-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Lung Li ,  Ping-Chia Shih ,  Wen-Peng Hsu ,  Chia-Wen Wang ,  Meng-Chun Chen ,  Chih-Hao Pan

IPC: H01L27/11568 ,  H01L29/423

Abstract: A non-volatile memory device includes a semiconductor substrate, a control gate electrode, a first oxide-nitride-oxide (ONO) structure, a selecting gate electrode, a second ONO structure, and a spacer structure. The control gate electrode and the selecting gate electrode are disposed on the semiconductor substrate. The first ONO structure is disposed between the control gate electrode and the semiconductor substrate. The second ONO structure is disposed between the control gate electrode and the selecting gate electrode in a first direction. The spacer structure is disposed between the control gate electrode and the second ONO structure in the first direction. A distance between the control gate electrode and the selecting gate electrode in the first direction is smaller than or equal to a sum of a width of the second ONO structure and a width of the spacer structure in the first direction.

公开(公告)号：US20180211966A1

公开(公告)日：2018-07-26

申请号：US15927914

申请日：2018-03-21

Applicant: United Microelectronics Corp.

Inventor： Chia-Wen Wang ,  Hsiang-Chen Lee ,  Wen-Peng Hsu ,  Kuo-Lung Li ,  Meng-Chun Chen ,  Zi-Jun Liu ,  Ping-Chia Shih

IPC: H01L27/1157 ,  H01L21/28 ,  H01L29/66 ,  H01L27/11573 ,  H01L27/11543 ,  H01L29/792 ,  H01L27/11563 ,  H01L29/78

CPC classification number: H01L27/1157 ,  H01L27/11543 ,  H01L27/11563 ,  H01L27/11573 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/7881 ,  H01L29/792

Abstract: A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.

公开(公告)号：US20180053771A1

公开(公告)日：2018-02-22

申请号：US15238574

申请日：2016-08-16

Applicant: United Microelectronics Corp.

Inventor： Chia-Wen Wang ,  Hsiang-Chen Lee ,  Wen-Peng Hsu ,  Kuo-Lung Li ,  Meng-Chun Chen ,  Zi-Jun Liu ,  Ping-Chia Shih

IPC: H01L27/115 ,  H01L29/792 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L27/1157 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11543 ,  H01L27/11563 ,  H01L27/11573 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/7881 ,  H01L29/792

Abstract: A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.

公开(公告)号：US20250113488A1

公开(公告)日：2025-04-03

申请号：US18494747

申请日：2023-10-25

Applicant: United Microelectronics Corp.

Inventor： Chia-Wen Wang ,  Chien-Hung Chen ,  Chia-Hui Huang ,  Ling Hsiu Chou ,  Jen Yang Hsueh ,  Chih-Yang Hsu

IPC: H10B43/30

Abstract: Provided are a memory structure and a manufacturing method thereof. The memory structure includes a substrate having first and second regions, first and second isolation structures in the substrate, a charge storage layer on the substrate, first and second gates and doped regions. The first isolation structures define first active areas in the first region. A top surface of the first isolation structure is higher than that of the substrate. The second isolation structures define second active areas in the second region. A top surface of the second isolation structure is lower than that of the substrate. The first gate is on the charge storage layer in the first active area. The second gate is on the charge storage layer in the second active area. The doped regions are in the substrate at two sides of the first gate and at two sides of the second gate.

公开(公告)号：US12119053B2

公开(公告)日：2024-10-15

申请号：US17680264

申请日：2022-02-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Wen Wang ,  Chien-Hung Chen ,  Chia-Hui Huang ,  Jen-Yang Hsueh ,  Ling-Hsiu Chou ,  Chih-Yang Hsu

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C11/5628 ,  G11C16/10 ,  G11C16/3427 ,  G11C16/3459 ,  G11C16/0483

Abstract: When programming an MLC memory device, the disturb characteristics of a program block having multiple memory cells are measured, and the threshold voltage variations of the multiple memory cells are then acquired based on the disturb characteristics of the program block. Next, multiple initial program voltage pulses are provided according to a predetermined signal level, and multiple compensated program voltage pulses are provided by adjusting the multiple initial program voltage pulses. Last, the multiple compensated program voltage pulses are outputted to the program block for programming the multiple memory cells to the predetermined signal level.

公开(公告)号：US20240114688A1

公开(公告)日：2024-04-04

申请号：US17990738

申请日：2022-11-21

Applicant: United Microelectronics Corp.

Inventor： Chia-Wen Wang ,  Chien-Hung Chen ,  Chia-Hui Huang ,  Ling Hsiu Chou ,  Jen Yang Hsueh ,  Chih-Yang Hsu

IPC: H10B43/30 ,  H10B41/30

CPC classification number: H01L27/11568 ,  H01L27/11521

Abstract: A memory structure including a substrate, a first doped region, a second doped region, a first gate, a second gate, a first charge storage structure, and a second charge storage structure is provided. The first gate is located on the first doped region. The second gate is located on the second doped region. The first charge storage structure is located between the first gate and the first doped region. The first charge storage structure includes a first tunneling dielectric layer, a first dielectric layer, and a first charge storage layer. The second charge storage structure is located between the second gate and the second doped region. The second charge storage structure includes a second tunneling dielectric layer, a second dielectric layer, and a second charge storage layer. The thickness of the second tunneling dielectric layer is greater than the thickness of the first tunneling dielectric layer.

公开(公告)号：US11532716B2

公开(公告)日：2022-12-20

申请号：US16793930

申请日：2020-02-18

Applicant: United Microelectronics Corp.

Inventor： Chia-Wen Wang ,  Chien-Hung Chen ,  Chia-Hui Huang ,  Jen Yang Hsueh ,  Ling Hsiu Chou ,  Chih-Yang Hsu

IPC: H01L29/423 ,  H01L27/11521 ,  H01L29/51 ,  H01L29/788 ,  H01L21/762 ,  H01L21/28 ,  H01L29/66 ,  G11C16/16 ,  G11C16/14

Abstract: A non-volatile memory device includes a substrate. A plurality of shallow trench isolation (STI) lines are disposed on the substrate and extend along a first direction. A memory gate structure is disposed on the substrate between adjacent two of the plurality of STI lines. A trench line is disposed in the substrate and extends along a second direction intersecting the first direction, wherein the trench line also crosses top portions of the plurality of STI lines. A conductive line is disposed in the trench line and used as a selection line to be coupled to the memory gate structure.

公开(公告)号：US20220278123A1

公开(公告)日：2022-09-01

申请号：US17700522

申请日：2022-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Wen Wang

IPC: H01L27/11568 ,  H01L29/792 ,  H01L29/66

Abstract: A semiconductor device includes a substrate having thereon at least one active area and at least one trench isolation region adjacent to the at least one active area. A charge trapping structure is disposed on the at least one active area and at least one trench isolation region. At least one divot is disposed in the at least one trench isolation region adjacent to the charge trapping structure. A silicon oxide layer is disposed in the at least one divot. A gate oxide layer is disposed on the at least one active area around the charge trapping structure.

公开(公告)号：US11362102B1

公开(公告)日：2022-06-14

申请号：US17185995

申请日：2021-02-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Wen Wang

IPC: H01L27/11568 ,  H01L29/66 ,  H01L29/792

Abstract: A semiconductor device includes a substrate having thereon at least one active area and at least one trench isolation region adjacent to the at least one active area. A charge trapping structure is disposed on the at least one active area and at least one trench isolation region. At least one divot is disposed in the at least one trench isolation region adjacent to the charge trapping structure. A silicon oxide layer is disposed in the at least one divot. A gate oxide layer is disposed on the at least one active area around the charge trapping structure.

公开(公告)号：US20210217866A1

公开(公告)日：2021-07-15

申请号：US16793930

申请日：2020-02-18

Applicant: United Microelectronics Corp.

Inventor： Chia-Wen Wang ,  Chien-Hung Chen ,  Chia-Hui Huang ,  Jen Yang Hsueh ,  Ling Hsiu Chou ,  Chih-Yang Hsu

IPC: H01L29/423 ,  H01L27/11521 ,  H01L29/51 ,  H01L21/762 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788

Abstract: A non-volatile memory device includes a substrate. A plurality of shallow trench isolation (STI) lines are disposed on the substrate and extend along a first direction. A memory gate structure is disposed on the substrate between adjacent two of the plurality of STI lines. A trench line is disposed in the substrate and extends along a second direction intersecting the first direction, wherein the trench line also crosses top portions of the plurality of STI lines. A conductive line is disposed in the trench line and used as a selection line to be coupled to the memory gate structure.