公开(公告)号：US20240413106A1

公开(公告)日：2024-12-12

申请号：US18350755

申请日：2023-07-12

Applicant: United Microelectronics Corp.

Inventor： Chien-Ming Lai

IPC: H01L23/00 ,  H01L25/065

Abstract: A semiconductor device includes a substrate, a bonding structure and an adjustment layer. A bonding structure is located over the substrate. The adjustment layer is located on a bonding pad of the bonding structure.

公开(公告)号：US11088285B2

公开(公告)日：2021-08-10

申请号：US16154644

申请日：2018-10-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ming Lai ,  Yen-Chen Chen ,  Jen-Po Huang ,  Sheng-Yao Huang ,  Hui-Ling Chen ,  Qinggang Xing ,  Ding-Lung Chen ,  Li Li Ding ,  Yao-Hung Liu

IPC: H01L29/76 ,  H01L29/786 ,  H01L29/66 ,  H01L29/51 ,  H01L29/423 ,  H01L29/49 ,  H01L29/10

Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.

公开(公告)号：US10446689B1

公开(公告)日：2019-10-15

申请号：US16274190

申请日：2019-02-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jen-Po Huang ,  Chien-Ming Lai ,  Yen-Chen Chen ,  Sheng-Yao Huang ,  Hui-Ling Chen ,  Seng Wah Liau ,  Han Chuan Fang

IPC: H01L29/768 ,  H01L29/417 ,  H01L29/66 ,  H01L21/4757 ,  H01L29/786

Abstract: An oxide semiconductor device includes a substrate, a first patterned oxide semiconductor layer, a source electrode, a drain electrode, and a sidewall spacer. The first patterned oxide semiconductor layer is disposed on the substrate. The source electrode and the drain electrode are disposed on the first patterned oxide semiconductor layer. The sidewall spacer is disposed on a sidewall of the first patterned oxide semiconductor layer. The sidewall spacer may be used to improve the performance of blocking impurities from entering the first patterned oxide semiconductor layer via the sidewall, and the electrical performance and the reliability of the oxide semiconductor device may be enhanced accordingly.

公开(公告)号：US10446688B1

公开(公告)日：2019-10-15

申请号：US16190090

申请日：2018-11-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jen-Po Huang ,  Chien-Ming Lai ,  Yen-Chen Chen ,  Sheng-Yao Huang ,  Hui-Ling Chen ,  Seng Wah Liau ,  Han Chuan Fang

IPC: H01L29/786 ,  H01L29/417 ,  H01L21/4757 ,  H01L29/66

Abstract: An oxide semiconductor device includes a substrate, a first patterned oxide semiconductor layer, a source electrode, a drain electrode, and a sidewall spacer. The first patterned oxide semiconductor layer is disposed on the substrate. The source electrode and the drain electrode are disposed on the first patterned oxide semiconductor layer. The sidewall spacer is disposed on a sidewall of the first patterned oxide semiconductor layer. The sidewall spacer may be used to improve the performance of blocking impurities from entering the first patterned oxide semiconductor layer via the sidewall, and the electrical performance and the reliability of the oxide semiconductor device may be enhanced accordingly.

公开(公告)号：US20160093616A1

公开(公告)日：2016-03-31

申请号：US14526552

申请日：2014-10-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ming Lai ,  Chien-Chung Huang ,  Yu-Ting Tseng ,  Ya-Huei Tsai ,  Yu-Ping Wang

IPC: H01L27/092 ,  H01L29/49 ,  H01L21/28 ,  H01L21/8238

CPC classification number: H01L21/823437 ,  H01L21/28088 ,  H01L21/283 ,  H01L21/3211 ,  H01L21/32139 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

Abstract: The present invention provides a complementary metal oxide semiconductor device, comprising a PMOS and an NMOS. The PMOS has a P type metal gate, which comprises a bottom barrier layer, a P work function metal (PWFM) layer, an N work function tuning (NWFT) layer, an N work function metal (NWFM) layer and a metal layer. The NMOS has an N type metal gate, which comprises the NWFT layer, the NWFM layer and the low-resistance layer. The present invention further provides a method of forming the same.

Abstract translation: 本发明提供一种互补金属氧化物半导体器件，其包括PMOS和NMOS。 PMOS具有P型金属栅极，其包括底部阻挡层，P功函数金属（PWFM）层，N功函数调整（NWFT）层，N功函数金属（NWFM）层和金属层。 NMOS具有N型金属栅极，其包括NWFT层，NWFM层和低电阻层。 本发明还提供一种形成该方法的方法。

公开(公告)号：US09129985B2

公开(公告)日：2015-09-08

申请号：US13784839

申请日：2013-03-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chao Tsao ,  Chien-Ting Lin ,  Chien-Ming Lai ,  Chi-Mao Hsu

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/32115 ,  H01L21/823842 ,  H01L27/0922 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78 ,  H01L29/7833

Abstract: A manufacturing method of semiconductor devices having metal gate includes following steps. A substrate having a first semiconductor device and a second semiconductor device formed thereon is provided. The first semiconductor device includes a first gate trench and the second semiconductor device includes a second gate trench. A first work function metal layer is formed in the first gate trench and the second gate trench. A portion of the first work function metal layer is removed from the second gate trench. A second work function metal layer is formed in the first gate trench and the second gate trench. The second work function metal layer and the first work function metal layer include the same metal material. A third work function metal layer and a gap-filling metal layer are sequentially formed in the first gate trench and the second gate trench.

Abstract translation: 具有金属栅极的半导体器件的制造方法包括以下步骤。 提供了具有形成在其上的第一半导体器件和第二半导体器件的衬底。 第一半导体器件包括第一栅极沟槽，第二半导体器件包括第二栅极沟槽。 在第一栅极沟槽和第二栅极沟槽中形成第一功函数金属层。 第一功函数金属层的一部分从第二栅极沟槽去除。 在第一栅极沟槽和第二栅极沟槽中形成第二功函数金属层。 第二功函数金属层和第一功函数金属层包括相同的金属材料。 在第一栅极沟槽和第二栅极沟槽中依次形成第三功函数金属层和间隙填充金属层。

公开(公告)号：US20140252423A1

公开(公告)日：2014-09-11

申请号：US13784839

申请日：2013-03-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chao Tsao ,  Chien-Ting Lin ,  Chien-Ming Lai ,  Chi-Mao Hsu

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/32115 ,  H01L21/823842 ,  H01L27/0922 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78 ,  H01L29/7833

Abstract: A manufacturing method of semiconductor devices having metal gate includes following steps. A substrate having a first semiconductor device and a second semiconductor device formed thereon is provided. The first semiconductor device includes a first gate trench and the second semiconductor device includes a second gate trench. A first work function metal layer is formed in the first gate trench and the second gate trench. A portion of the first work function metal layer is removed from the second gate trench. A second work function metal layer is formed in the first gate trench and the second gate trench. The second work function metal layer and the first work function metal layer include the same metal material. A third work function metal layer and a gap-filling metal layer are sequentially formed in the first gate trench and the second gate trench.

Abstract translation: 具有金属栅极的半导体器件的制造方法包括以下步骤。 提供了具有形成在其上的第一半导体器件和第二半导体器件的衬底。 第一半导体器件包括第一栅极沟槽，第二半导体器件包括第二栅极沟槽。 第一功函数金属层形成在第一栅极沟槽和第二栅极沟槽中。 第一功函数金属层的一部分从第二栅极沟槽去除。 在第一栅极沟槽和第二栅极沟槽中形成第二功函数金属层。 第二功函数金属层和第一功函数金属层包括相同的金属材料。 在第一栅极沟槽和第二栅极沟槽中依次形成第三功函数金属层和间隙填充金属层。

公开(公告)号：US11342465B2

公开(公告)日：2022-05-24

申请号：US17140114

申请日：2021-01-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ming Lai ,  Yen-Chen Chen ,  Jen-Po Huang ,  Sheng-Yao Huang ,  Hui-Ling Chen ,  Qinggang Xing ,  Ding-Lung Chen ,  Li Li Ding ,  Yao-Hung Liu

IPC: H01L29/76 ,  H01L29/786 ,  H01L29/66 ,  H01L29/51 ,  H01L29/423 ,  H01L29/49 ,  H01L29/10

Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.

公开(公告)号：US11164822B1

公开(公告)日：2021-11-02

申请号：US17035385

申请日：2020-09-28

Applicant: United Microelectronics Corp.

Inventor： Chung-Hsing Kuo ,  Chun-Ting Yeh ,  Ming-Tse Lin ,  Hui-Ling Chen ,  Chien-Ming Lai

IPC: H01L23/544 ,  H01L23/488 ,  H01L23/00

Abstract: A structure of semiconductor device is provided. The structure includes a first bonding pattern, formed on a first substrate. A first grating pattern is disposed on the first substrate, having a plurality of first bars extending along a first direction. A second bonding pattern is formed on a second substrate. A second grating pattern, disposed on the second substrate, having a plurality of second bars extending along the first direction. The first bonding pattern is bonded to the second bonding pattern. One of the first grating pattern and the second grating pattern is stacked over and overlapping at the first direction with another one of the first grating pattern and the second grating pattern. A first gap between adjacent two of the first bars is different from a second gap between adjacent two of the second bars.

公开(公告)号：US20200083380A1

公开(公告)日：2020-03-12

申请号：US16154644

申请日：2018-10-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ming Lai ,  Yen-Chen Chen ,  Jen-Po Huang ,  Sheng-Yao Huang ,  Hui-Ling Chen ,  Qinggang Xing ,  Ding-Lung Chen ,  Li Li Ding ,  Yao-Hung Liu

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/10 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51

Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.