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    MAGNETIC TUNNEL JUNCTION (MTJ) DEVICE AND FORMING METHOD THEREOF
    2.
    发明申请
    MAGNETIC TUNNEL JUNCTION (MTJ) DEVICE AND FORMING METHOD THEREOF 有权

    公开(公告)号：US20230091364A1

    公开(公告)日：2023-03-23

    申请号：US18073574

    申请日：2022-12-02

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wei Chen ,  Hui-Lin Wang ,  Yu-Ru Yang ,  Chin-Fu Lin ,  Yi-Syun Chou ,  Chun-Yao Yang

    IPC: H01L27/22 ,  H01L23/552 ,  H01L43/10 ,  H01F41/34 ,  H01L43/02 ,  G11C11/16 ,  H01F10/32 ,  H01L43/12

    Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.

    MAGNETIC TUNNEL JUNCTION (MTJ) DEVICE AND FORMING METHOD THEREOF
    3.
    发明申请
    MAGNETIC TUNNEL JUNCTION (MTJ) DEVICE AND FORMING METHOD THEREOF 审中-公开

    公开(公告)号：US20200227471A1

    公开(公告)日：2020-07-16

    申请号：US16261584

    申请日：2019-01-30

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wei Chen ,  Hui-Lin Wang ,  Yu-Ru Yang ,  Chin-Fu Lin ,  Yi-Syun Chou ,  Chun-Yao Yang

    IPC: H01L27/22 ,  H01L23/552 ,  H01L43/10 ,  H01L43/12 ,  H01L43/02 ,  G11C11/16 ,  H01F10/32 ,  H01F41/34

    Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.

    CAPACITOR STRUCTURE AND MANUFACTURING METHOD THEREOF
    4.
    发明申请
    CAPACITOR STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20180130871A1

    公开(公告)日：2018-05-10

    申请号：US15346717

    申请日：2016-11-08

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hung-Chan Lin ,  Chin-Fu Lin ,  Chun-Yuan Wu

    IPC: H01L49/02

    CPC classification number: H01L28/88

    Abstract: The present invention provides a capacitor structure, including a bottom plate and a top plate, wherein the top plate has a first sidewall, and wherein an area of the top plate is less than an area of the bottom plate. The capacitor structure further includes a dielectric layer in between the bottom plate and the top plate, the dielectric layer having a second sidewall, wherein the first sidewall is aligned with the second sidewall, and at least one sidewall spacer placed against the first sidewall of the top plate and the second sidewall of the dielectric layer, and overlaying a portion of the bottom plate.

    SEMICONDUCTOR DEVICE HAVING STRAINED FIN STRUCTURE AND METHOD OF MAKING THE SAME
    7.
    发明申请
    SEMICONDUCTOR DEVICE HAVING STRAINED FIN STRUCTURE AND METHOD OF MAKING THE SAME 有权
    具有应变熔体结构的半导体器件及其制造方法

    公开(公告)号：US20150348971A1

    公开(公告)日：2015-12-03

    申请号：US14825165

    申请日：2015-08-12

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Teng-Chun Tsai ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Cheng Chien ,  Chin-Fu Lin

    IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/165

    CPC classification number: H01L21/845 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/165

    Abstract: A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate.

    Abstract translation: 半导体器件包括半导体衬底，至少第一鳍结构，至少第二鳍结构，第一栅极，第二栅极，第一源极/漏极区域和第二源极/漏极区域。 半导体衬底至少具有第一有源区以配置第一鳍结构和至少第二有源区以配置第二鳍结构。 与第一/第二栅极部分重叠的第一/第二鳍结构具有第一/第二应力，第一应力和第二应力彼此不同。 第一/第二源极/漏极区域设置在第一/第二栅极的两侧的第一/第二鳍结构中。

    THROUGH SILICON VIA (TSV) PROCESS
    8.
    发明申请
    THROUGH SILICON VIA (TSV) PROCESS 有权
    通过硅（TSV）工艺

    公开(公告)号：US20150340280A1

    公开(公告)日：2015-11-26

    申请号：US14817227

    申请日：2015-08-04

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Jia-Jia Chen ,  Chi-Mao Hsu ,  Tsun-Min Cheng ,  Chun-Ling Lin ,  Huei-Ru Tsai ,  Ching-Wei Hsu ,  Chin-Fu Lin ,  Hsin-Yu Chen

    IPC: H01L21/768

    CPC classification number: H01L21/76847 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a conductive layer. The barrier layer covers a surface of the recess. The buffer layer covers the barrier layer. The conductive layer is located on the buffer layer and fills the recess, wherein the contact surface between the conductive layer and the buffer layer is smoother than the contact surface between the buffer layer and the barrier layer. Moreover, a through silicon via process forming said through silicon via structure is also provided.

    Abstract translation: 硅通孔结构位于衬底的凹槽中。 贯通硅通孔结构包括阻挡层，缓冲层和导电层。 阻挡层覆盖凹部的表面。 缓冲层覆盖阻挡层。 导电层位于缓冲层上并填充凹槽，其中导电层和缓冲层之间的接触表面比缓冲层和阻挡层之间的接触表面更平滑。 此外，还提供了形成所述贯穿硅通孔结构的通硅通孔工艺。

    Semiconductor device
    9.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09130032B2

    公开(公告)日：2015-09-08

    申请号：US14465579

    申请日：2014-08-21

    Applicant: United Microelectronics Corp.

    Inventor： Hsin-Fu Huang ,  Kun-Hsien Lin ,  Chi-Mao Hsu ,  Min-Chuan Tsai ,  Tzung-Ying Lee ,  Chin-Fu Lin

    IPC: H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L29/51

    CPC classification number: H01L29/78 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

    Abstract: Provided is a semiconductor device including a substrate, a gate structure, a second dielectric layer and a source/drain region. A first dielectric layer is disposed on the substrate, and the first dielectric layer has a trench therein. The gate structure is disposed on the substrate in the trench and includes a work function metal layer and a metal layer. The work function metal layer is disposed in the trench, and includes a TiAl3 phase metal layer. A height of the work function metal layer disposed on a sidewall of the trench is lower than a height of a top surface of the first dielectric layer. The metal layer fills the trench. The second dielectric layer is disposed between the gate structure and the substrate. The source/drain region is disposed in the substrate at two sides of the gate structure.

    Abstract translation: 提供了一种包括基板，栅极结构，第二介电层和源极/漏极区域的半导体器件。 第一电介质层设置在基板上，并且第一介电层在其中具有沟槽。 栅极结构设置在沟槽中的衬底上，并且包括功函数金属层和金属层。 工作功能金属层设置在沟槽中，并且包括TiAl 3相金属层。 布置在沟槽的侧壁上的功函数金属层的高度低于第一电介质层的顶表面的高度。 金属层填充沟槽。 第二电介质层设置在栅极结构和衬底之间。 源极/漏极区域在栅极结构的两侧设置在衬底中。

    METHOD FOR FORMING A FINFET STRUCTURE
    10.
    发明申请
    METHOD FOR FORMING A FINFET STRUCTURE 审中-公开
    形成FINFET结构的方法

    公开(公告)号：US20150132966A1

    公开(公告)日：2015-05-14

    申请号：US14583813

    申请日：2014-12-29

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hung-Lin Shih ,  Jei-Ming Chen ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Kuan-Hsien Li

    IPC: H01L21/8234 ,  H01L29/40

    CPC classification number: H01L21/30604 ,  H01L21/823431 ,  H01L21/823462 ,  H01L29/401

    Abstract: A method for forming a FinFET structure includes providing a substrate, a first region and a second region being defined on the substrate, a first fin structure and a second fin structure being disposed on the substrate within the first region and the second region respectively. A first oxide layer cover the first fin structure and the second fin structure. Next a first protective layer and a second protective layer are entirely formed on the substrate and the first oxide layer in sequence, the second protective layer within the first region is removed, and the first protective layer within the first region is then removed. Afterwards, the first oxide layer covering the first fin structure and the second protective layer within the second region are removed simultaneously, and a second oxide layer is formed to cover the first fin structure.

    Abstract translation: 一种用于形成FinFET结构的方法包括提供衬底，第一区和限定在衬底上的第二区，分别在第一区和第二区内的衬底上设置第一鳍结构和第二鳍结构。 第一氧化物层覆盖第一鳍结构和第二鳍结构。 接下来，依次在基板和第一氧化物层上完全形成第一保护层和第二保护层，去除第一区域内的第二保护层，然后去除第一区域内的第一保护层。 之后，同时除去覆盖第二区域内的第一鳍结构和第二保护层的第一氧化物层，形成第二氧化物层以覆盖第一鳍结构。

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