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公开(公告)号：US10811272B2
公开(公告)日：2020-10-20
申请号：US16261578
申请日：2019-01-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wei-Hsin Liu , Ta-Wei Chiu , Chia-Lung Chang , Po-Chun Chen , Hong-Yi Fang , Yi-Wei Chen
IPC: H01L21/3105 , H01L21/027 , H01L21/02 , H01L21/311 , H01L21/3213 , H01L27/108 , H01L29/66
Abstract: A method of forming a dielectric layer includes the following steps. A substrate including a first area and a second area is provided. A plurality of patterns on the substrate of the first area and a blanket stacked structure on the substrate of the second area are formed. An organic dielectric layer covers the patterns, the blanket stacked structure and the substrate. The blanket stacked structure is patterned by serving the organic dielectric layer as a hard mask layer, thereby forming a plurality of stacked structures. The organic dielectric layer is removed. A dielectric layer blanketly covers the patterns, the stacked structures, and the substrate.
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公开(公告)号：US20190280095A1
公开(公告)日：2019-09-12
申请号：US15943717
申请日：2018-04-03
Inventor： Po-Chun Chen , Chia-Lung Chang , Yi-Wei Chen , Wei-Hsin Liu , Han-Yung Tsai
IPC: H01L29/423 , H01L21/762 , H01L27/108 , H01L21/28
Abstract: A method for fabricating semiconductor device includes the steps of: forming a shallow trench isolation (STI) in the substrate; removing part of the STI to form a trench in a substrate; forming an amorphous silicon layer in the trench and on the STI; performing an oxidation process to transform the amorphous silicon layer into a silicon dioxide layer; and forming a barrier layer and a conductive layer in the trench.
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公开(公告)号：US10276650B2
公开(公告)日：2019-04-30
申请号：US15927103
申请日：2018-03-21
Inventor： Tzu-Chin Wu , Wei-Hsin Liu , Yi-Wei Chen , Chia-Lung Chang , Jui-Min Lee , Po-Chun Chen , Li-Wei Feng , Ying-Chiao Wang , Wen-Chieh Lu , Chien-Ting Ho , Tsung-Ying Tsai , Kai-Ping Chen
IPC: H01L27/108 , H01L49/02 , H01L29/94
Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.
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公开(公告)号：US20200243541A1
公开(公告)日：2020-07-30
申请号：US16841694
申请日：2020-04-07
Inventor： Kun-Hsin Chen , Hsuan-Tung Chu , Tsuo-Wen Lu , Po-Chun Chen
IPC: H01L27/108 , H01L21/762 , H01L21/02 , H01L29/06
Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a periphery region; forming a first trench and a second trench in substrate on the memory region, in which a width of the second trench is greater than a width of the first trench; forming a first liner in the first trench and the second trench; forming a second liner on the first liner as the second liner completely fills the first trench and partly fills the second trench; and planarizing the second liner and the first liner to form a first isolation structure and a second isolation structure.
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公开(公告)号：US10468417B2
公开(公告)日：2019-11-05
申请号：US15959291
申请日：2018-04-23
Inventor： Chih-Chien Liu , Tzu-Chin Wu , Po-Chun Chen , Chia-Lung Chang
IPC: H01L23/48 , H01L27/108 , H01L21/02 , H01L21/8234
Abstract: A fabricating method of a stop layer includes providing a substrate. The substrate is divided into a memory region and a peripheral circuit region. Two conductive lines are disposed within the peripheral circuit region. Then, an atomic layer deposition is performed to form a silicon nitride layer to cover the conductive lines. Later, after forming the silicon nitride layer, a silicon carbon nitride layer is formed to cover the silicon nitride layer. The silicon carbon nitride layer serves as a stop layer.
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Patent Agency Ranking
公开(公告)号：US10249706B1
公开(公告)日：2019-04-02
申请号：US15951185
申请日：2018-04-12
Inventor： Chia-Lung Chang , Wei-Hsin Liu , Po-Chun Chen , Yi-Wei Chen , Han-Yung Tsai , Tzu-Chin Wu , Shih-Fang Tzou
IPC: H01L49/02 , H01L27/108
Abstract: The present invention provides a semiconductor structure comprising a substrate, a cell region defined on the substrate, a plurality of lower electrodes of the capacitor structures located in the cell region, an top support structure, contacting a top region of the lower electrode structure, and at least one middle support structure located between the substrate and the top support structure, contacting a middle region of the lower electrode structure, wherein when viewed in a top view, the top support structure and the middle support structure do not completely overlapped with each other.
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公开(公告)号：US20140106568A1
公开(公告)日：2014-04-17
申请号：US14142940
申请日：2013-12-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Yuan Wu , Chih-Chien Liu , Chin-Fu Lin , Po-Chun Chen
IPC: H01L21/311
CPC classification number: H01L21/31144 , H01L21/76802
Abstract: The present invention provides a method of forming an opening on a semiconductor substrate. First, a substrate is provided. Then a dielectric layer and a cap layer are formed on the substrate. A ratio of a thickness of the dielectric layer and a thickness of the cap layer is substantially between 15 and 1.5. Next, a patterned boron nitride layer is formed on the cap layer. Lastly, an etching process is performed by using the patterned hard mask as a mask to etch the cap layer and the dielectric layer so as to form an opening in the cap layer and the dielectric layer.
Abstract translation: 本发明提供一种在半导体衬底上形成开口的方法。 首先，提供基板。 然后在基板上形成介电层和盖层。 电介质层的厚度和盖层的厚度之比基本上在15和1.5之间。 接下来，在盖层上形成图案化的氮化硼层。 最后，通过使用图案化的硬掩模作为掩模来执行蚀刻工艺，以蚀刻覆盖层和电介质层，以在盖层和电介质层中形成开口。
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公开(公告)号：US11133320B2
公开(公告)日：2021-09-28
申请号：US16841694
申请日：2020-04-07
Inventor： Kun-Hsin Chen , Hsuan-Tung Chu , Tsuo-Wen Lu , Po-Chun Chen
IPC: H01L27/108 , H01L21/762 , H01L21/02 , H01L29/06
Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a periphery region; forming a first trench and a second trench in substrate on the memory region, in which a width of the second trench is greater than a width of the first trench; forming a first liner in the first trench and the second trench; forming a second liner on the first liner as the second liner completely fills the first trench and partly fills the second trench; and planarizing the second liner and the first liner to form a first isolation structure and a second isolation structure.
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公开(公告)号：US20200227269A1
公开(公告)日：2020-07-16
申请号：US16261578
申请日：2019-01-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wei-Hsin Liu , Ta-Wei Chiu , Chia-Lung Chang , Po-Chun Chen , Hong-Yi Fang , Yi-Wei Chen
IPC: H01L21/3105 , H01L27/108 , H01L21/027 , H01L29/66 , H01L21/311 , H01L21/3213 , H01L21/02
Abstract: A method of forming a dielectric layer includes the following steps. A substrate including a first area and a second area is provided. A plurality of patterns on the substrate of the first area and a blanket stacked structure on the substrate of the second area are formed. An organic dielectric layer covers the patterns, the blanket stacked structure and the substrate. The blanket stacked structure is patterned by serving the organic dielectric layer as a hard mask layer, thereby forming a plurality of stacked structures. The organic dielectric layer is removed. A dielectric layer blanketly covers the patterns, the stacked structures, and the substrate.
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公开(公告)号：US20200075397A1
公开(公告)日：2020-03-05
申请号：US16134982
申请日：2018-09-19
Inventor： Po-Chun Chen , Hsuan-Tung Chu , Yi-Wei Chen , Wei-Hsin Liu , Yu-Cheng Tung , Chia-Lung Chang
IPC: H01L21/762 , H01L21/02
Abstract: A method of forming an isolation structure includes the following steps. A substrate having a first trench, a second trench and a third trench is provided, wherein the opening of the third trench is larger than the opening of the second trench, and the opening of the second trench is larger than the opening of the first trench. A first oxide layer is formed to conformally cover the first trench, the second trench and the third trench by an atomic layer deposition (ALD) process. A second oxide layer fills up the first trench by an in-situ steam generation (ISSG) process.
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