公开(公告)号：US10177231B2

公开(公告)日：2019-01-08

申请号：US15797011

申请日：2017-10-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hung Chen ,  Shih-Hsien Huang ,  Yu-Ru Yang ,  Huai-Tzu Chiang ,  Hao-Ming Lee ,  Sheng-Hao Lin ,  Cheng-Tzung Tsai ,  Chun-Yuan Wu

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L21/306 ,  H01L29/165 ,  H01L21/3065

Abstract: A semiconductor device comprises a semiconductor substrate and a semiconductor fin. The semiconductor substrate has an upper surface and a recess extending downwards into the semiconductor substrate from the upper surface. The semiconductor fin is disposed in the recess and extends upwards beyond the upper surface, wherein the semiconductor fin is directly in contact with semiconductor substrate, so as to form at least one semiconductor hetero-interface on a sidewall of the recess.

公开(公告)号：US09837493B2

公开(公告)日：2017-12-05

申请号：US14940867

申请日：2015-11-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hung Chen ,  Shih-Hsien Huang ,  Yu-Ru Yang ,  Huai-Tzu Chiang ,  Hao-Ming Lee ,  Sheng-Hao Lin ,  Cheng-Tzung Tsai ,  Chun-Yuan Wu

IPC: H01L29/165 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/165 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device comprises a semiconductor substrate and a semiconductor fin. The semiconductor substrate has an upper surface and a recess extending downwards into the semiconductor substrate from the upper surface. The semiconductor fin is disposed in the recess and extends upwards beyond the upper surface, wherein the semiconductor fin is directly in contact with semiconductor substrate, so as to form at least one semiconductor hetero-interface on a sidewall of the recess.

公开(公告)号：US20170117414A1

公开(公告)日：2017-04-27

申请号：US14941674

申请日：2015-11-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Hsien Huang ,  Chien-Hung Chen ,  Chun-Yuan Wu ,  Kun-Hsin Chen ,  Tien-I Wu ,  Yu-Ru Yang ,  Huai-Tzu Chiang

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/06 ,  H01L21/324 ,  H01L29/66 ,  H01L29/167 ,  H01L29/10

CPC classification number: H01L29/66795 ,  H01L21/324 ,  H01L21/823412 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/167 ,  H01L29/785 ,  H01L29/7851 ,  H01L2029/7858 ,  H01L2924/13067

Abstract: A semiconductor structure including a semiconductor substrate and at least a fin structure formed thereon. The semiconductor substrate includes a first semiconductor material. The fin structure includes a first epitaxial layer and a second epitaxial layer formed between the first epitaxial layer and the semiconductor substrate. The first epitaxial layer includes the first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is different from a lattice constant of the first semiconductor material. The second epitaxial layer includes the first semiconductor material and the second semiconductor material. The second epitaxial layer further includes conductive dopants.

公开(公告)号：US20160181383A1

公开(公告)日：2016-06-23

申请号：US14613343

申请日：2015-02-03

Applicant: United Microelectronics Corp.

Inventor： Shih-Hsien Huang ,  Che-Wei Chang ,  Chih-Chieh Yeh ,  Tzu-I Tsai

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/08 ,  H01L21/285 ,  H01L21/302 ,  H01L29/66 ,  H01L29/45

CPC classification number: H01L29/41791 ,  H01L21/28518 ,  H01L21/302 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/41758 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: The present invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor device includes a substrate, an epitaxial structure, and a recess. The epitaxial structure is disposed in the substrate. The recess is formed in the epitaxial structure, where the recess has a cross-section in a direction perpendicular to the substrate, and at least one portion of the recess is gradually expanded from an opening of the recess.

Abstract translation: 半导体器件及其制造方法技术领域本发明涉及半导体器件及其制造方法。 半导体器件包括衬底，外延结构和凹部。 外延结构设置在基板中。 凹槽形成在外延结构中，其中凹部在垂直于衬底的方向上具有横截面，并且凹部的至少一部分从凹部的开口逐渐膨胀。

公开(公告)号：US10068963B2

公开(公告)日：2018-09-04

申请号：US14936370

申请日：2015-11-09

Applicant: United Microelectronics Corp.

Inventor： Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Hao-Ming Lee ,  Yu-Ru Yang ,  Shih-Hsien Huang ,  Chien-Hung Chen ,  Chun-Yuan Wu ,  Cheng-Tzung Tsai

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/161 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L21/225 ,  H01L21/768

Abstract: Provided is a FinFET including a substrate, at least one fin and at least one gate. A portion of the at least one fin is embedded in the substrate. The at least one fin includes, from bottom to top, a seed layer, a stress relaxation layer and a channel layer. The at least one gate is across the at least one fin. A method of forming a FinFET is further provided.

公开(公告)号：US09590041B1

公开(公告)日：2017-03-07

申请号：US14960430

申请日：2015-12-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ru Yang ,  Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Shih-Hsien Huang ,  Chien-Hung Chen ,  Chun-Yuan Wu ,  Cheng-Tzung Tsai

IPC: H01L21/02 ,  H01L29/10 ,  H01L29/78 ,  H01L29/165 ,  H01L29/778 ,  H01L27/092

CPC classification number: H01L29/1054 ,  H01L21/02381 ,  H01L21/02538 ,  H01L27/092 ,  H01L29/105 ,  H01L29/66795 ,  H01L29/778 ,  H01L29/785

Abstract: A semiconductor structure includes a semiconductor substrate, a dielectric structure formed on the semiconductor substrate and including at least a recess formed therein, a fin formed in the recess, and a dislocation region formed in the fin. The semiconductor substrate includes a first semiconductor material. The fin includes the first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is different from a lattice constant of the first semiconductor material. A topmost portion of the dislocation region is higher than an opening of the recess.

Abstract translation: 半导体结构包括半导体衬底，形成在半导体衬底上并且至少包括形成在其中的凹部的电介质结构，形成在凹部中的鳍和形成在鳍中的位错区。 半导体衬底包括第一半导体材料。 翅片包括第一半导体材料和第二半导体材料。 第二半导体材料的晶格常数与第一半导体材料的晶格常数不同。 位错区域的最高部分高于凹部的开口。

公开(公告)号：US10573649B2

公开(公告)日：2020-02-25

申请号：US15045258

申请日：2016-02-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hung Chen ,  Shih-Hsien Huang ,  Yu-Ru Yang ,  Chia-Hsun Tseng ,  Cheng-Tzung Tsai ,  Chun-Yuan Wu

IPC: H01L27/092 ,  H01L29/165 ,  H01L21/8238 ,  H01L29/10 ,  H01L21/02 ,  H01L29/737

Abstract: A semiconductor device includes a substrate, a first well formed in the substrate, a second well formed in the substrate, a first fin formed on the first well, and a second fin formed on the second well. The first well includes a first conductivity type, the second well includes a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other. The substrate includes a first semiconductor material. The first fin and the second fin include the first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The first semiconductor material in the first fin includes a first concentration, the first semiconductor material in the second fin includes a second concentration, and the second concentration is larger than the first concentration.

公开(公告)号：US10439023B2

公开(公告)日：2019-10-08

申请号：US16040319

申请日：2018-07-19

Applicant: United Microelectronics Corp.

Inventor： Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Hao-Ming Lee ,  Yu-Ru Yang ,  Shih-Hsien Huang ,  Chien-Hung Chen ,  Chun-Yuan Wu ,  Cheng-Tzung Tsai

IPC: H01L29/76 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L21/225 ,  H01L21/768

Abstract: Provided is a FinFET including a substrate, at least one fin and at least one gate. A portion of the at least one fin is embedded in the substrate. The at least one fin includes, from bottom to top, a seed layer, a stress relaxation layer and a channel layer. The at least one gate is across the at least one fin. A method of forming a FinFET is further provided.

公开(公告)号：US09741852B2

公开(公告)日：2017-08-22

申请号：US14818487

申请日：2015-08-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Hsien Huang ,  Tsang-Hsuan Wang ,  James Tsai

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/66636

Abstract: A manufacturing method of a semiconductor structure is provided. The manufacturing method of the semiconductor structure includes the following steps: providing a substrate; forming a gate structure on the substrate; forming a recess in the substrate at a lateral side of the gate structure; performing a pre-bake process at a temperature of 740-840° C. and under a pressure of equal to or higher than 150 torr; and forming an epitaxial buffer layer in the recess.

公开(公告)号：US20170104070A1

公开(公告)日：2017-04-13

申请号：US14940867

申请日：2015-11-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hung Chen ,  Shih-Hsien Huang ,  Yu-Ru Yang ,  Huai-Tzu Chiang ,  Hao-Ming Lee ,  Sheng-Hao Lin ,  Cheng-Tzung Tsai ,  Chun-Yuan Wu

IPC: H01L29/165 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/06 ,  H01L21/02

CPC classification number: H01L29/165 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device comprises a semiconductor substrate and a semiconductor fin. The semiconductor substrate has an upper surface and a recess extending downwards into the semiconductor substrate from the upper surface. The semiconductor fin is disposed in the recess and extends upwards beyond the upper surface, wherein the semiconductor fin is directly in contact with semiconductor substrate, so as to form at least one semiconductor hetero-interface on a sidewall of the recess.