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    Vertical cross-point arrays for ultra-high-density memory applications
    1.
    发明授权
    Vertical cross-point arrays for ultra-high-density memory applications 有权

    公开(公告)号：US11849593B2

    公开(公告)日：2023-12-19

    申请号：US17840385

    申请日：2022-06-14

    Applicant: Unity Semiconductor Corporation

    Inventor： Bruce Lynn Bateman

    IPC: H01L45/00 ,  H10B63/00 ,  H10N70/20 ,  H10N70/00

    CPC classification number: H10B63/845 ,  H10B63/22 ,  H10B63/34 ,  H10N70/24 ,  H10N70/823 ,  H10N70/826 ,  H10N70/8833 ,  H10N70/8836

    Abstract: An ultra-high-density vertical cross-point array comprises a plurality of horizontal line layers having horizontal lines interleaved with a plurality of vertical lines arranged in rows and columns. The vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer. Each vertical line comprises a center conductor surrounded by a single or multi-layered memory film. Accordingly, when interleaved with the horizontal lines, two-terminal memory cells are integrally formed between the center conductor of each vertical line and each crossing horizontal line. By configuring the vertical and horizontal lines so that a row of vertical lines is positioned between each consecutive pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

    Vertical cross-point arrays for ultra-high-density memory applications
    2.
    发明授权
    Vertical cross-point arrays for ultra-high-density memory applications 有权

    公开(公告)号：US11367751B2

    公开(公告)日：2022-06-21

    申请号：US16948575

    申请日：2020-09-23

    Applicant: Unity Semiconductor Corporation

    Inventor： Bruce Lynn Bateman

    IPC: H01L45/02 ,  H01L27/24 ,  H01L45/00

    Abstract: An ultra-high-density vertical cross-point array comprises a plurality of horizontal line layers having horizontal lines interleaved with a plurality of vertical lines arranged in rows and columns. The vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer. Each vertical line comprises a center conductor surrounded by a single or multi-layered memory film. Accordingly, when interleaved with the horizontal lines, two-terminal memory cells are integrally formed between the center conductor of each vertical line and each crossing horizontal line. By configuring the vertical and horizontal lines so that a row of vertical lines is positioned between each consecutive pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

    Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations
    6.
    发明授权
    Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations 有权
    全局位线预充电电路，用于补偿过程，工作电压和温度变化

    公开(公告)号：US09117495B2

    公开(公告)日：2015-08-25

    申请号：US13935105

    申请日：2013-07-03

    Applicant: UNITY SEMICONDUCTOR CORPORATION

    Inventor： Chang Hua Siau ,  Bruce Lynn Bateman

    IPC: G11C5/06 ,  G11C5/08 ,  G11C7/00 ,  G11C7/18 ,  G11C13/00 ,  G11C7/04 ,  G11C7/12 ,  G11C16/24

    CPC classification number: G11C5/06 ,  G11C5/08 ,  G11C7/00 ,  G11C7/04 ,  G11C7/12 ,  G11C7/18 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/24 ,  G11C2213/71

    Abstract: A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.

    Abstract translation: 存储器阵列包括字线，本地位线，双端存储器元件，全局位线以及局部到全局位线传递门​​和增益级。 存储元件形成在字线和本地位线之间。 每个本地位线通过相关联的局部到全局位线传递门​​选择性地耦合到相关联的全局位线。 在选择本地位线的存储元件被读取的读取操作期间，局部到全局增益级被配置为将本地位线上的信号放大到相关联的全局位线上或沿相关联的全局位线 。 在一个实施例中放大的信号取决于所选择的存储器元件的电阻状态，被用于快速地确定由所选择的存储器元件存储的存储器状态。 全局位线和/或选定的局部位线可被偏置以补偿过程电压温度（PVT）变化。

    Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations
    8.
    发明授权
    Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations 有权

    公开(公告)号：US11087841B2

    公开(公告)日：2021-08-10

    申请号：US16784332

    申请日：2020-02-07

    Applicant: Unity Semiconductor Corporation

    Inventor： Chang Hua Siau ,  Bruce Lynn Bateman

    IPC: G11C11/00 ,  G11C13/00 ,  G11C7/04 ,  G11C7/00 ,  G11C16/24 ,  G11C7/12 ,  G11C5/08 ,  G11C7/18 ,  G11C5/06 ,  H01L27/10

    Abstract: A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.

    VERTICAL CROSS-POINT ARRAYS FOR ULTRA-HIGH-DENSITY MEMORY APPLICATIONS
    9.
    发明申请
    VERTICAL CROSS-POINT ARRAYS FOR ULTRA-HIGH-DENSITY MEMORY APPLICATIONS 有权

    公开(公告)号：US20210083005A1

    公开(公告)日：2021-03-18

    申请号：US16948575

    申请日：2020-09-23

    Applicant: Unity Semiconductor Corporation

    Inventor： Bruce Lynn Bateman

    IPC: H01L27/24 ,  H01L45/00

    Abstract: An ultra-high-density vertical cross-point array comprises a plurality of horizontal line layers having horizontal lines interleaved with a plurality of vertical lines arranged in rows and columns. The vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer. Each vertical line comprises a center conductor surrounded by a single or multi-layered memory film. Accordingly, when interleaved with the horizontal lines, two-terminal memory cells are integrally formed between the center conductor of each vertical line and each crossing horizontal line. By configuring the vertical and horizontal lines so that a row of vertical lines is positioned between each consecutive pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

    GLOBAL BIT LINE PRE-CHARGE CIRCUIT THAT COMPENSATES FOR PROCESS, OPERATING VOLTAGE, AND TEMPERATURE VARIATIONS
    10.
    发明申请
    GLOBAL BIT LINE PRE-CHARGE CIRCUIT THAT COMPENSATES FOR PROCESS, OPERATING VOLTAGE, AND TEMPERATURE VARIATIONS 审中-公开

    公开(公告)号：US20190279712A1

    公开(公告)日：2019-09-12

    申请号：US16297303

    申请日：2019-03-08

    Applicant: Unity Semiconductor Corporation

    Inventor： Chang Hua Siau ,  Bruce Lynn Bateman

    IPC: G11C13/00 ,  G11C5/06 ,  G11C7/04 ,  G11C7/00 ,  G11C16/24 ,  G11C7/12 ,  G11C5/08 ,  G11C7/18

    Abstract: A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.

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