公开(公告)号：US09905682B2

公开(公告)日：2018-02-27

申请号：US15372352

申请日：2016-12-07

Applicant: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA ,  INSTITUTE OF ELECTRONIC AND INFORMATION ENGINEERING IN DONGGUAN, UESTC

Inventor： Jinping Zhang ,  Zehong Li ,  Jingxiu Liu ,  Min Ren ,  Bo Zhang ,  Zhaoji Li

IPC: H01L29/74 ,  H01L29/78 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3065 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66 ,  H01L29/747

CPC classification number: H01L29/7424 ,  H01L21/02233 ,  H01L21/26586 ,  H01L21/3065 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/408 ,  H01L29/66325 ,  H01L29/66386 ,  H01L29/7394 ,  H01L29/747 ,  H01L29/78

Abstract: A bidirectional Metal-Oxide-Semiconductor (MOS) device, including a P-type substrate, and an active region. The active region includes a drift region, a first MOS structure and a second MOS structure; the first MOS structure includes a first P-type body region, a first P+ contact region, a first N+ source region, a first metal electrode, and a first gate structure; the second MOS structure includes a second P-type body region, a second P+ contact region, a second N+ source region, a second metal electrode, and a second gate structure; and the drift region includes a dielectric slot, a first N-type layer, a second N-type layer, and an N-type region. The active region is disposed on the upper surface of the P-type substrate. The first MOS structure and the second MOS structure are symmetrically disposed on two ends of the upper layer of the drift region.

公开(公告)号：US11888022B2

公开(公告)日：2024-01-30

申请号：US17744779

申请日：2022-05-16

Applicant: University of Electronic Science and Technology of China

Inventor： Wentong Zhang ,  Ning Tang ,  Ke Zhang ,  Nailong He ,  Ming Qiao ,  Zhaoji Li ,  Bo Zhang

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L29/0607 ,  H01L29/407 ,  H01L29/66325 ,  H01L29/66681 ,  H01L29/7394 ,  H01L29/7823 ,  H01L29/7824

Abstract: An SOI lateral homogenization field high voltage power semiconductor device, and a manufacturing method and application thereof are provided. The device includes a type I conductive semiconductor substrate, a type II conductive drift region, a type I field clamped layer, type I and type II conductive well regions, the first dielectric oxide layer forming a field oxide layer, the second dielectric oxide layer forming a gate oxide layer, a type II conductive buried dielectric layer, a type II conductive source heavily doped region, a type II conductive drain heavily doped region. The first dielectric oxide layer and the floating field plate polysilicon electrodes form a vertical floating field plate distributed throughout the type II conductive drift region to form a vertical floating equipotential field plate array. When the device is in on-state, high doping concentration can be realized by the full-region depletion effect form the vertical field plate arrays.