公开(公告)号：US09977738B2

公开(公告)日：2018-05-22

申请号：US15289893

申请日：2016-10-10

Applicant: VMware, Inc.

Inventor： Rajesh Venkatasubramanian ,  Puneet Zaroo ,  Alexandre Milouchev

IPC: G06F12/00 ,  G06F12/08 ,  G06F12/0891 ,  G06F9/50 ,  G06F9/455 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/1009 ,  G06F3/06 ,  G06F12/06 ,  G06F12/02 ,  G06F12/1072 ,  G06F12/0868 ,  G06F12/10

CPC classification number: G06F12/08 ,  G06F3/0604 ,  G06F3/0614 ,  G06F3/0662 ,  G06F3/0665 ,  G06F9/45558 ,  G06F9/5033 ,  G06F9/5083 ,  G06F12/0292 ,  G06F12/0638 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/10 ,  G06F12/1009 ,  G06F12/1072 ,  G06F2009/45583 ,  G06F2212/1016 ,  G06F2212/152 ,  G06F2212/2542 ,  G06F2212/6042 ,  G06F2212/62

Abstract: In a system having non-uniform memory access architecture, with a plurality of nodes, memory access by entities such as virtual CPUs is estimated by invalidating a selected sub-set of memory units, and then detecting and compiling access statistics, for example by counting the page faults that arise when any virtual CPU accesses an invalidated memory unit. The entities, or pairs of entities, may then be migrated or otherwise co-located on the node for which they have greatest memory locality.

公开(公告)号：US09465669B2

公开(公告)日：2016-10-11

申请号：US14201787

申请日：2014-03-07

Applicant: VMware, Inc.

Inventor： Rajesh Venkatasubramanian ,  Puneet Zaroo ,  Alexandre Milouchev

IPC: G06F12/00 ,  G06F9/50 ,  G06F12/10 ,  G06F3/06 ,  G06F12/06 ,  G06F12/02 ,  G06F12/08

CPC classification number: G06F12/08 ,  G06F3/0604 ,  G06F3/0614 ,  G06F3/0662 ,  G06F3/0665 ,  G06F9/45558 ,  G06F9/5033 ,  G06F9/5083 ,  G06F12/0292 ,  G06F12/0638 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/10 ,  G06F12/1009 ,  G06F12/1072 ,  G06F2009/45583 ,  G06F2212/1016 ,  G06F2212/152 ,  G06F2212/2542 ,  G06F2212/6042 ,  G06F2212/62

Abstract: In a system having non-uniform memory access architecture, with a plurality of nodes, memory access by entities such as virtual CPUs is estimated by invalidating a selected sub-set of memory units, and then detecting and compiling access statistics, for example by counting the page faults that arise when any virtual CPU accesses an invalidated memory unit. The entities, or pairs of entities, may then be migrated or otherwise co-located on the node for which they have greatest memory locality.

Abstract translation: 在具有不均匀的存储器访问架构的系统中，通过多个节点，通过使所选择的存储单元的子集失效，然后检测和编译访问统计信息来估计诸如虚拟CPU之类的实体的存储器访问，例如通过计数 任何虚拟CPU访问无效内存单元时出现的页面故障。 然后可以将实体或实体对迁移或以其他方式共同位于它们具有最大存储器位置的节点上。