公开(公告)号：US11947458B2

公开(公告)日：2024-04-02

申请号：US16048180

申请日：2018-07-27

Applicant: VMware LLC

Inventor： Irina Calciu ,  Jayneel Gandhi ,  Aasheesh Kolli ,  Pratap Subrahmanyam

IPC: G06F12/0817

CPC classification number: G06F12/0828 ,  G06F2212/152

Abstract: A device is connected via a coherence interconnect to a CPU with a cache. The device monitors cache coherence events via the coherence interconnect, where the cache coherence events relate to the cache of the CPU. The device also includes a buffer that can contain representations, such as addresses, of cache lines. If a coherence event occurs on the coherence interconnect indicating that a cache line in the CPU's cache is dirty, then the device is configured to add an entry to the buffer to record the dirty cache line.