公开(公告)号：US20230402361A1

公开(公告)日：2023-12-14

申请号：US17840322

申请日：2022-06-14

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： Shenghua Huang ,  Binbin Zheng ,  Shaopeng Dong ,  Songtao Lu ,  Rui Guo ,  Yangming Liu ,  Bo Yang ,  Ning Ye

IPC: H01L23/498 ,  H01L23/12 ,  H01L23/31 ,  H01L25/065 ,  G06K19/077 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/12 ,  H01L23/3107 ,  H01L25/0657 ,  G06K19/07732 ,  H01L24/48 ,  H01L2225/06562 ,  H01L2924/3512 ,  H01L2924/1511 ,  H01L2224/48135

Abstract: A semiconductor device includes a substrate, semiconductor dies on the substrate, molding compound and reinforcing blocks on the substrate. The reinforcing blocks may be provided at positions on the substrate where mechanical stresses develop in the device during singulation, such as at curves and/or discontinuous points around the outline of the substrate, to add strength to the substrate.

公开(公告)号：US20220406726A1

公开(公告)日：2022-12-22

申请号：US17354119

申请日：2021-06-22

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： Jiandi Du ,  Binbin Zheng ,  Rui Guo ,  Chin-Tien Chiu ,  Zengyu Zhou ,  Fen Yu

IPC: H01L23/552 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00

Abstract: A semiconductor device has shielding to prevent transmission and/or reception of EMI and/or RFI radiation. The semiconductor device comprises a substrate including grounded contact pads around a periphery of the substrate, exposed at one or more edges of the substrate. A bump made of gold or other non-oxidizing conductive material may be formed on the contact pads, for example using ultrasonic welding to remove an oxidation layer between the contact pads and the conductive bumps. The conductive bumps electrically couple to a conductive coating applied around the periphery of the semiconductor device.

公开(公告)号：US12193166B2

公开(公告)日：2025-01-07

申请号：US17719815

申请日：2022-04-13

Applicant: Western Digital Technologies, Inc.

Inventor： Songtao Lu ,  Hsiang Ju Huang ,  Binbin Zheng ,  Cheng-Hsiung Yang ,  Chien-Te Chen

IPC: H05K3/28 ,  H05K1/09

Abstract: In one example, the present application describes a Printed Circuit Board (PCB) that mitigates galvanic corrosion during an Organic Solderability Preservative (OSP) process used during fabrication of the PCB. The PCB includes a first metal pattern and a second metal pattern electrically coupled to each other, where the first and second metal patterns are different metals. The first metal pattern has a first area that is exposed by a solder mask layer, and the second metal pattern has a second area that is exposed by the solder mask area. A ratio of the first area to the second area is less than a threshold ratio to mitigate the galvanic corrosion of the second metal pattern exposed on the PCB during the OSP process.

公开(公告)号：US11784135B2

公开(公告)日：2023-10-10

申请号：US17354119

申请日：2021-06-22

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： Jiandi Du ,  Binbin Zheng ,  Rui Guo ,  Chin-Tien Chiu ,  Zengyu Zhou ,  Fen Yu

IPC: H01L23/552 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L23/552 ,  H01L23/49838 ,  H01L24/13 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/1357 ,  H01L2224/13144 ,  H01L2224/13647 ,  H01L2225/06506 ,  H01L2225/06537 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2924/3025

Abstract: A semiconductor device has shielding to prevent transmission and/or reception of EMI and/or RFI radiation. The semiconductor device comprises a substrate including grounded contact pads around a periphery of the substrate, exposed at one or more edges of the substrate. A bump made of gold or other non-oxidizing conductive material may be formed on the contact pads, for example using ultrasonic welding to remove an oxidation layer between the contact pads and the conductive bumps. The conductive bumps electrically couple to a conductive coating applied around the periphery of the semiconductor device.

公开(公告)号：US20220415750A1

公开(公告)日：2022-12-29

申请号：US17902641

申请日：2022-09-02

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： Jiandi Du ,  Yazhou Zhang ,  Binbin Zheng ,  Sundarraj Chandran ,  Wenbin Qu ,  Chin-Tien Chiu

IPC: H01L23/38 ,  H01L25/00 ,  H01L25/18 ,  H01L25/065

Abstract: A thermoelectric semiconductor device includes a heat dissipating semiconductor module and a stack of flash memory dies mounted on a substrate. The heat dissipating module comprises a first semiconductor die such as a controller, and a second semiconductor die such as a thermoelectric semiconductor die to cool the first semiconductor die during operation. The thermoelectric semiconductor die may be mounted to the controller die at the wafer level.

公开(公告)号：US11901260B2

公开(公告)日：2024-02-13

申请号：US17902641

申请日：2022-09-02

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： Jiandi Du ,  Yazhou Zhang ,  Binbin Zheng ,  Sundarraj Chandran ,  Wenbin Qu ,  Chin-Tien Chiu

IPC: H01L23/38 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L23/38 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2225/06506 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/06589

Abstract: A thermoelectric semiconductor device includes a heat dissipating semiconductor module and a stack of flash memory dies mounted on a substrate. The heat dissipating module comprises a first semiconductor die such as a controller, and a second semiconductor die such as a thermoelectric semiconductor die to cool the first semiconductor die during operation. The thermoelectric semiconductor die may be mounted to the controller die at the wafer level.

公开(公告)号：US20230337372A1

公开(公告)日：2023-10-19

申请号：US17719815

申请日：2022-04-13

Applicant: Western Digital Technologies, Inc.

Inventor： Songtao Lu ,  Hsiang Ju Huang ,  Binbin Zheng ,  Cheng-Hsiung Yang ,  Chien-Te Chen

IPC: H05K3/28 ,  H05K1/09

CPC classification number: H05K3/282 ,  H05K1/09 ,  H05K2203/0591

Abstract: In one example, the present application describes a Printed Circuit Board (PCB) that mitigates galvanic corrosion during an Organic Solderability Preservative (OSP) process used during fabrication of the PCB. The PCB includes a first metal pattern and a second metal pattern electrically coupled to each other, where the first and second metal patterns are different metals. The first metal pattern has a first area that is exposed by a solder mask layer, and the second metal pattern has a second area that is exposed by the solder mask area. A ratio of the first area to the second area is less than a threshold ratio to mitigate the galvanic corrosion of the second metal pattern exposed on the PCB during the OSP process.

公开(公告)号：US11444001B1

公开(公告)日：2022-09-13

申请号：US17314712

申请日：2021-05-07

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： Jiandi Du ,  Yazhou Zhang ,  Binbin Zheng ,  Sundarraj Chandran ,  Wenbin Qu ,  Chin-Tien Chiu

IPC: H01L23/38 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: A thermoelectric semiconductor device includes a heat dissipating semiconductor module and a stack of flash memory dies mounted on a substrate. The heat dissipating module comprises a first semiconductor die such as a controller, and a second semiconductor die such as a thermoelectric semiconductor die to cool the first semiconductor die during operation. The thermoelectric semiconductor die may be mounted to the controller die at the wafer level.