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公开(公告)号：US20240193088A1
公开(公告)日：2024-06-13
申请号：US18231730
申请日：2023-08-08
Applicant: Western Digital Technologies, Inc.
Inventor： Chao Sun , Qingbo Wang , Minghai Qin , Jaco Hofmann , Anand Kulkarni , Dejan Vucinic , Zvonimir Bandic
IPC: G06F12/0862 , G06N20/00
CPC classification number: G06F12/0862 , G06N20/00
Abstract: A memory device includes a first memory and a second memory that caches data stored in the first memory. At least one controller of the memory device receives page fault information from a host. The page fault information results from a request for data by the host that is stored in the first memory but is not cached in the second memory when requested by the host. The memory device uses the received page fault information for one or more inputs into a prefetch model trained by Machine Learning (ML) to generate at least one inference. Based at least in part on the at least one inference, prefetch data is cached in the second memory. In one aspect, the page fault information is used to train the prefetch model. In another aspect, the page fault information includes at least one virtual address used by the host for the requested data.
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公开(公告)号：US20240119055A1
公开(公告)日：2024-04-11
申请号：US18449116
申请日：2023-08-14
Applicant: Western Digital Technologies, Inc.
Inventor： Chao Sun , Muqing Liu , Yan Li , Dejan Vucinic
IPC: G06F16/245
CPC classification number: G06F16/24569
Abstract: Various devices, such as storage devices or storage systems are configured to perform on device semantic searching. The device includes a processor, a plurality of memory devices, a controller coupled to the memory devices, and an intelligent memory array logic. The intelligent memory array logic is configured to receive a query, extract contextual data from the query, determine a machine learning model for processing the query based on the extracted contextual data, generate a query vector based on the query and determined machine learning model, determine one or more relevant memory structures associated with the generated query vector, and pass in the query vector to the one or more determined relevant memory structures. The one or more relevant memory structures include feature data and one or more machine learning processing units configured to process the query vector and feature data to generate a comparison value.
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3.发明授权公开(公告)号：US11782642B2
公开(公告)日：2023-10-10
申请号：US17347457
申请日：2021-06-14
Applicant: Western Digital Technologies, Inc.
Inventor： Chao Sun , Tung Thanh Hoang , Dejan Vucinic
CPC classification number: G06F3/0659 , G06F3/0616 , G06F3/0619 , G06F3/0673 , G06F11/1068
Abstract: Certain aspects of the present disclosure provide techniques for performing compute in memory (CIM) computations. A device comprises a CIM module configured to apply a plurality of analog weights to data using multiply-accumulate operations to generate an output. The device further comprises a digital weight storage unit configured to store digital weight references, wherein a digital weight reference corresponds to an analog weight of the plurality of analog weights. The device also comprises a device controller configured to program the plurality of analog weights to the CIM module based on the digital weight references and determine degradation of one or more analog weights. The digital weight references in the digital weight storage unit are populated with values from a host device. Degraded analog weights in the CIM module are replaced with corresponding digital weight references from the digital weight storage unit without reference to the host device.
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公开(公告)号：US11106534B2
公开(公告)日：2021-08-31
申请号：US16287251
申请日：2019-02-27
Applicant: Western Digital Technologies, Inc.
Inventor： Chao Sun , Pi-Feng Chiu , Dejan Vucinic
Abstract: An apparatus is disclosed having a parity buffer having a plurality of parity pages and one or more dies, each die having a plurality of layers in which data may be written. The apparatus also includes a storage controller configured to write a stripe of data across two or more layers of the one or more dies, the stripe having one or more data values and a parity value. When a first data value of the stripe is written, it is stored as a currant value in a parity page of the parity buffer, the parity page corresponding to the stripe. For each subsequent data value that is written, an XOR operation is performed with the subsequent data value and the current value of the corresponding parity page and the result of the XOR operation is stored as the current value of the corresponding parity page.
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公开(公告)号：US20210194829A1
公开(公告)日：2021-06-24
申请号：US16724226
申请日：2019-12-21
Applicant: Western Digital Technologies, Inc.
Inventor： Chao Sun , Pietro Bressana , Dejan Vucinic
IPC: H04L12/931 , H04L29/08 , H04L29/06
Abstract: A programmable network switch includes at least one pipeline including a packet parser configured to parse packets, and a plurality of ports for communication with network devices including a plurality of Data Storage Devices (DSDs). A packet comprising a write command is received to store data in a DSD of the plurality of DSDs, and an identifier generated for the data is compared to a plurality of identifiers generated for data stored in the plurality of DSDs. It is determined whether to send the write command to store the data to the DSD based on whether the generated identifier matches an identifier of the plurality of identifiers. In one aspect, the data to be stored for the write command is extracted from the packet using a pipeline of the programmable network switch, and at least a portion of the extracted data is used to generate the identifier for the data.
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Patent Agency Ranking
公开(公告)号：US10373528B2
公开(公告)日：2019-08-06
申请号：US15379216
申请日：2016-12-14
Applicant: Western Digital Technologies, Inc.
Inventor： Zvonimir Z. Bandic , Robert Eugeniu Mateescu , Minghai Qin , Chao Sun
Abstract: The present disclosure generally relates to a method of burning a file in a memory device after the file has been read. Once a file has been read, an algorithm uses the memory device to create errors that the error correction code (ECC) cannot decode the error. In creating the error, the entire word line is destroyed physically rather than logically so that retrieving information from that particular word line is no longer possible. In creating the error, adjacent word lines are not affected. The error renders the file burned.
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公开(公告)号：US10360973B2
公开(公告)日：2019-07-23
申请号：US15472326
申请日：2017-03-29
Applicant: Western Digital Technologies, Inc.
Inventor： Zvonimir Z. Bandic , Robert Eugeniu Mateescu , Minghai Qin , Chao Sun
Abstract: In this disclosure, data mapping based on three dimensional lattices that have an improved sum rate (i.e., lifetime capacity) with low read latency is disclosed. During the write, a memory location is written to multiple times prior to erasure. Specifically, for the first write, there are 4/3 bits per cell available for writing, which is about 10.67 kB per cell are used for data storage. Then, for the second write, there is one bit per cell, which is 8 kB per cell for data storage. If considering a block with 128 different cells and writing 32 kB of data, the first write results in 42.66 data writes while the second write results in 32 writes for a total of 74.66 writes. Previously, the number of writes for 32 kB would be 64 writes. Thus, by writing twice prior to erasure, more data can be stored.
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8.发明申请公开(公告)号：US20180329815A1
公开(公告)日：2018-11-15
申请号：US15590789
申请日：2017-05-09
Applicant: Western Digital Technologies, Inc.
Inventor： Seung-hwan Song , Won Ho Choi , Chao Sun , Dejan Vucinic
IPC: G06F12/02 , G06F12/0831 , G06F12/127 , G06F13/16 , G11C16/04
CPC classification number: G06F12/0246 , G06F12/02 , G06F12/0215 , G06F12/0833 , G06F12/127 , G06F13/1689 , G11C5/04 , G11C7/00 , G11C8/12 , G11C16/0441
Abstract: A storage system is provided comprising a controller and a memory comprising a plurality of tiles of memory organized in a plurality of tile groups, wherein a given tile group is busy when any tile in the given tile group is busy. The controller is configured to: inform the host of the busy status of the plurality of tile groups; receive a plurality of commands from the host, wherein each command is provided with a different tile group identifier of a tile group that is not busy; and execute the plurality of commands, wherein because each command comprises a different tile group identifier of a tile group that is not busy, the plurality of commands are executed in parallel.
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公开(公告)号：US10067683B2
公开(公告)日：2018-09-04
申请号：US15214185
申请日：2016-07-19
Applicant: Western Digital Technologies, Inc.
Inventor： Viacheslav Dubeyko , Chao Sun
Abstract: Systems and methods for writing data to a storage are disclosed. The disclosed systems and methods can receive, by a target device in communication with a host, a first write request from the host to write first data to the storage in communication with the target device. The disclosed systems and methods can determine, by a storage controller in the target device, a data type of the first data based on a first flag set corresponding to the first data. The disclosed systems and methods can store the first data to a location in the storage based at least on the data type of the first data.
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公开(公告)号：US09912352B1
公开(公告)日：2018-03-06
申请号：US15614914
申请日：2017-06-06
Applicant: Western Digital Technologies, Inc.
Inventor： Minghai Qin , Chao Sun , Dejan Vucinic
CPC classification number: H03M7/6035 , H03M7/02 , H03M7/24 , H03M13/00
Abstract: Technology is described herein for encoding and decoding numbers. In one aspect, floating point numbers are represented as binary strings. The binary strings may be encoded in a manner such that if one bit flips, the average and maximum distortion in the number that is represented by the binary string is relatively small. In one aspect, 2^n binary strings are ordered across an interval [a, b) in accordance with their Hamming weights. Numbers in the interval may be uniformly quantized into one of 2^n sub-intervals. For example, floating point numbers in the interval [a, b) may be uniformly quantized into 2^n sub-intervals. These 2^n sub-intervals may be mapped to the 2^n binary strings. Thus, the number may be assigned to one of the 2^n binary strings. Doing so may reduce the distortion in the number in the event that there is a bit flip in the assigned binary string.
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